有两个职位的描述要求进行了更新，如下：
其中ASIC Physical Design Engineer招得非常急，各位大牛有兴趣就出手啊
GPU ASIC Physical Design engineer
As a senior member of our ASIC-PD team, you'll be working on streamlining the chip infrastructure process across product designs, focusing on full chip layout planning (partitioning, planning clock distribution and other structure, methodology), partition/full chip timing closure (primetime scripts, other tools, etc) and gate-level design of high-speed logic
RESPONSIBILITIES: - Chip integration and netlist generation -Synthesis, Formal verification, netlist quality check - Work in conjunction with Place and Route Engineers to achieve timing closure for both partition level and full chip level
- Develop and enhance entire timing flow from frontend (pre-layout) to backend (post-layout) at both chip and block level.
- Develop custom timing scripts using tcl/primetime for clock skew analysis, special circuits such as clock dividers, core logic <-> IO macros interfaces such as PCI-E, Frame-Buffer/Memory, TMDS, etc.
- Develop flow to physically partition and floorplan the entire chip.
- Develop scripts for performing ECO's.
MINIMUM REQUIREMENTS:
- BS or MS in Electrical Engineering or Computer Science
- Above 3 years of relevant ASIC experience ideally with a focus in the chip integration /synthesis/formal and timing closure
- Excellent scripts skills - Excellent written and verbal communication skills in English - Ability to multiplex many issues, set priorities, and work in a team environment - Keep up to date with leading edge technologies
Sr. ASIC Design Project Lead (SoC) Job Description/Qualifications: RESPONSIBILITIES: - ASIC Design/Verification for graphics and video processors. - Definition of world-class chip configures - Debug and fix SOC level issues - Maintain/Develop the working environment - Working closely with video / graphics and other sub-unit designers. - Support backend team’s work as the bridge between frontend and backend - RTL design, verification, emulation, synthesis, timing, and silicon bring-up. MINIMUM REQUIREMENTS: - ASIC / Logic Design engineers with previous experience in Video, Graphics, Microprocessor Design, SOC design, or Multimedia ASIC design. - Be familiar with chip level verification and debugging - Strong logic design and verification skills. - Verilog and Synopsys experience required. Primetime experience desirable. - Programming skills in C and PERL. - Good communication skills and proven ability to work well within a team. - The ideal candidate will be familiar with all aspects of the frontend ASIC design flow including RTL design, verification, synthesis, and timing analysis - BS in Electronic Engineering, MS preferred. | 
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发表于 2012-2-1 17:46:38
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