Chapter 1. The Case for a New SOC Design Methodology
Section 1.1. The Age of Megagate SOCs
Section 1.2. The Fundamental Trends of SOC Design
Section 1.3. What's Wrong with Today's Approach to SOC Design?
Section 1.4. Preview: An Improved Design Methodology for SOC Design
Section 1.5. Further Reading
Chapter 2. SOC Design Today
Section 2.1. Hardware System Structure
Section 2.2. Software Structure
Section 2.3. Current SOC Design Flow
Section 2.4. The Impact of Semiconductor Economics
Section 2.5. Six Major Issues in SOC Design
Section 2.6. Further Reading
Chapter 3. A New Look at SOC Design
Section 3.1. The Basics of Processor-Centric SOC Architecture
Section 3.2. Accelerating Processors for Traditional Software Tasks
Section 3.3. Example: Tensilica Xtensa Processors for EEMBC Benchmarks
Section 3.4. System Design with Multiple Processors
Section 3.5. New Essentials of SOC Design Methodology
Section 3.6. Addressing the Six Problems
Section 3.7. Further Reading
Chapter 4. System-Level Design of Complex SOCs
Section 4.1. Complex SOC System Architecture Opportunities
Section 4.2. Major Decisions in Processor-Centric SOC Organization
Section 4.3. Communication Design = Software Mode + Hardware Interconnect
Section 4.4. Hardware Interconnect Mechanisms
Section 4.5. Performance-Driven Communication Design
Section 4.6. The SOC Design Flow
Section 4.7. Non-Processor Building Blocks in Complex SOC
Section 4.8. Implications of Processor-Centric SOC Architecture
Section 4.9. Further Reading
Chapter 5. Configurable Processors: A Software View
Section 5.1. Processor Hardware/Software Cogeneration
Section 5.2. The Process of Instruction Definition and Application Tuning
Section 5.3. The Basics of Instruction Extension
Section 5.4. The Programmer's Model
Section 5.5. Processor Performance Factors
Section 5.6. Example: Tuning a Large Task
Section 5.7. Memory-System Tuning
Section 5.8. Long Instruction Words
Section 5.9. Fully Automatic Instruction-Set Extension
Section 5.10. Further Reading
Chapter 6. Configurable Processors: A Hardware View
Section 6.1. Application Acceleration: A Common Problem
Section 6.2. Introduction to Pipelines and Processors
Section 6.3. Hardware Blocks to Processors
Section 6.4. Moving from Hardwired Engines to Processors
Section 6.5. Designing the Processor Interface
Section 6.6. A Short Example: ATM Packet Segmentation and Reassembly
Section 6.7. Novel Roles for Processors in Hardware Replacement
Section 6.8. Processors, Hardware Implementation and Verification Flow
Section 6.9. Progress in Hardware Abstraction
Section 6.10. Further Reading
Chapter 7. Advanced Topics in SOC Design
Section 7.1. Pipelining for Processor Performance
Section 7.2. Inside Processor Pipeline Stalls
Section 7.3. Optimizing Processors to Match Hardware
Section 7.4. Multiple Processor Debug and Trace
Section 7.5. Issues in Memory Systems
Section 7.6. Optimizing Power Dissipation in Extensible Processors
Section 7.7. Essentials of TIE
Section 7.8. Further Reading
Chapter 8. The Future of SOC Design: The Sea of Processors
Section 8.1. What's Happening to SOC Design?
Section 8.2. Why Is Software Programmability So Central?
Section 8.3. Looking into the Future of SOC
Section 8.4. Processor Scaling Model
Section 8.5. Future Applications of Complex SOCs
Section 8.6. The Future of the Complex SOC Design Process
Section 8.7. The Future of the Industry
Section 8.8. The Disruptive-Technology View
Section 8.9. The Long View
Section 8.10. Further Reading
/2 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2011-12-29 19:19:14
