|
马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。
您需要 登录 才可以下载或查看,没有账号?注册
x
Hi, all
plz help with the following formality troubles
In my design, I have some empty ports(which are finally not used, and are kept given the current project stage),
however when doing formal-check(REF: synthesis netlist, IMP: route netlist), troubles are issued.
eg. the empty port "PORT_0" are matched point and are verified, however the following unmatched points are issued
Ref Und REF:/WORK/design/PORT_O(1 reference, 0 implementation)
do I need to care this, or how to fix it?
thanks in advance
regards,
henry |
|