在线咨询
eetop公众号 创芯大讲堂 创芯人才网
切换到宽版

EETOP 创芯网论坛 (原名:电子顶级开发网)

手机号码,快捷登录

手机号码,快捷登录

找回密码

  登录   注册  

快捷导航
搜帖子
EETOP诚邀模拟IC相关培训讲师 创芯人才网--重磅上线啦!
查看: 2458|回复: 3

[招聘] 职业机会 Analog/mixed signal IC design 知名美资企业

[复制链接]
发表于 2011-12-16 10:05:56 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

x
Job 1 Title: Sr. Staff engineer, Analog/mixed signal IC design (wireless team)

Main Responsibilities:

1.Technical lead of the wireless team in China designing analog blocks such as PLL, ADC, DAC, Filter, Regulator, SERDES
2.Corner Simulations (Cadence, Spectre, Ocean, Monte Carlo, ADS)
3.Layout design
4.Block/chip level verification (LVS, DRC, LPE)
5.Design review
6.Chip level integration
7.Test, characterization, debug
8.Close work with US team including occasional travel
9.Helping other team members with their design/schedule

Job Requirements:

1.MSEE with at least 10 years of industry experience
2.Previous leadership experience is a plus
3.Deep understanding of fundamental analog techniques
4.Experience with low-power analog design in deep submicron CMOS
5.Experience in Cadence Spectre, SpectreRF, AMS and Virtuoso
6.Hands-on experience in analog layout design and verification
7.Knowledge of Skill, Matlab & verilog programming
8.Experience with high volume IC manufacturing is a plus
9.Hands-on experience with lab equipment
10.Occasional travel to US for technical training/design review/product test

Job 2 Title: Staff engineer, Analog/mixed signal IC design (wireless team)

Main Responsibilities:

1.Independent design of analog blocks such as bandgap reference, voltage   regulator, bias and understanding of other blocks such as PLL, ADC, DAC, SERDES
2.Corner Simulations (Cadence, Spectre, Ocean, Monte Carlo, ADS)
3.Layout design
4.Block/chip level verification (LVS, DRC, LPE)
5.Design review
6.Chip level integration
7.Test, characterization, debug
8.Close work with US team including occasional travel

Job Requirements:

1.MSEE with at least 5 years of industry experience
2.Good understanding of fundamental analog techniques
3.Experience with low-power analog design in deep submicron CMOS
4.Experience in Cadence Spectre, SpectreRF, AMS and Virtuoso
5.Hands-on experience in analog layout design and verification
6.Knowledge of Skill, Matlab & verilog programming is a plus
7.Experience with high volume IC manufacturing is a plus
8.Hands-on experience with lab equipment
9.Occasional travel to US for technical training/design review/product test
 楼主| 发表于 2011-12-16 10:07:43 | 显示全部楼层
如对此职位感兴趣可加MSN:jennifer_wxx@msn.cn 了解联系情况,

或发送邮件至:job606@green-information.com
发表于 2011-12-23 14:38:43 | 显示全部楼层
帮顶楼主~~~看来IC设计还是很有发展前途的~~~~
 楼主| 发表于 2011-12-23 15:58:12 | 显示全部楼层
非常谢谢
您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐 上一条 /1 下一条

小黑屋| 手机版| 关于我们| 联系我们| 在线咨询| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2024-11-18 03:18 , Processed in 0.021128 second(s), 9 queries , Gzip On, Redis On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表