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本帖最后由 icfbicfb 于 2011-11-30 09:18 编辑
如果analog layouter能这么灵活，就不需要太多的custom layout ，
像数字的place&route 一样，自动化的流程，我相信，最后这一天肯定会来，
就是不知道啥时候，
My last IC design at Intel was a Graphics Chip and I developed a layout generator for Programmable Logic Arrays (PLA) that automated the task, so I've always been interested in how to make IC layout more push-button and less polygon pushing. Today I watched a video about HiPer DevGen from Tanner EDA and wanted to share what I learned. This technology came from IC Mask, a Dublin-based services and training company.
HiPer DevGen has a focus on accelerating analog layout while giving the designer control over the process. Analog generators have been developed for: - Current Mirrors
- Differential Pairs
- Resistor Dividers
Using these layout generators will get you quickly into a layout that is correct by construction and that looks like hand-crafted layout. The layout generators are silicon-aware and use double contacts and vias as appropriate for a given technology node, also taking into account: - Linear process gradients
- Mask misalignment
- Implant shadowing
- Shallow Trench Isolation (STI)
- Length of Diffusion (LOD)
- Lithography invariance
- Current flow direction
- Antenna effect, Vt shift
- Well Proximity Effect (WPE)
The design flow shown below starts with schematic capture that infers analog structures that will be automated with HiPer DevGen, then the designer uses Schematic Driven Placement and does manual placement adjustments as needed along with automated or manual routing.
Technology setup is done with a GUI and you can type in your layout rules in about 20 minutes for a new process node, or just ask if this is already available for the foundry you've selected:
OpAmp Example
A simple 11 transistor netlist was used that had differential pairs, current mirrors and other transistors:
With Schematic Driven Layout and HiPer DevGen you quickly get a layout with five instances that correspond to your schematic:
In a few minutes you can change the aspect ratio of each layout block and re-position the placement of each block to reach a more optimal layout.
Within 10 minutes the OpAmp has been placed and routed, no mismatches, and with correct-by-construction layout that is DRC and LVS clean:
Using the old-fashioned way of manual analog layout this same design would take you a half day to two full days to get DRC and LVS clean.
Linear Process Gradient
Analog circuits are sensitive to process variations as a function of layout position, so one layout technique to combat this is called Common Centroid. Shown below are devices A and B that have been split up into two areas as Common Centroid where process gradient effects are minimized:
Another benefit of using the Common Centroid layout approach is that it minimizes the effects of mask misalignment:
A current mirror with Common Centroid layout was created by HiPer DevGen using a dialog box in the GUI:
Edge Effects
Polysilicon etch rates depend on how closely spaced poly lines are drawn. Show below is an area where poly edges on the outsides of three devices has been etched more than on the insides of the devices, resulting in performance mismatch:
To minimize edge effects the layout generators place dummy devices on the outside of the active devices:
Complex Current Mirror
Another example of Common Centroid layout was shown with a four-transistor current mirror design:
The same current mirror was then changed into two rows to achieve a different aspect ratio:
Differential Pair
The layout generator GUI for a differential pair was used to create a Common Centroid layout, and there are over a dozen parameters that you get to control based on your unique objectives:
The antenna effect is mitigated by choosing the option Add Protection Diodes.
STI Effects
Stress effects like Shallow Trench Isolation cause mismatch in transistors as show below where the center MOS device has 25% more stress than the outer devices:
Clicking a checkbox for STI Matching then produces a layout that mitigates stress effects:
Comparison versus Competitors
Cadence has the most mature layout automation technology around called Pcells using SKILL code. Most foundries support the Cadence PDK.
Competitors to Cadence have allied around the concept of Interoperable Process Development Kits (iPDKs). Tanner EDA has joined this alliance and is gradually migrating their tools to support iPDK.
Synopsys offers a tool called Galaxy Custom Designer to automate layout generation.
Mentor Graphics provides the Pyxis Layout Suite to support layout generators.
Ciranova supports analog layout automation with the Helix tools using PyCells based on the Python language.
Magma has a set of Titan FlexCell Libraries.
SpringSoft has created Magic Cell (MCell) for parameterized device generation.
Analog Rails is a smaller company with tools for automating analog layout.
Summary
Accelerating analog layout for IC designers has become much quicker and easy to use with HiPer DevGen from Tanner EDA. These EDA tools have a lower price tag than what you'll find at the public EDA companies and I've found the company very responsive to answering my questions. Here's the HiPer DevGen webinar video, White Paper at EE Times, and a PowerPoint presentation from DAC 2010.
There are plenty of competitors out there offering analog layout automation tools, so you'll have to evaluate which one is the best fit based on: how much control you want, the time to learn, legacy designs, technology node, fab recommendations, experience, and your budget. |
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发表于 2011-11-30 09:16:57
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