A 1.0-V, 10-Bit CMOS Pipelined Analog-to-Digital Converter

hi_china59

Abstract
With the explosive growth of wireless communication systems and portable
consumer electronics, the demand for low-power low-voltage integrated circuits (ICs)
is indispensable. Many of the applications nowadays utilize the digital signal
processing to resolve the transmitted information. Therefore, between the received
analog signal and the DSP system, an analog-to-digital interface is required. Being a
part of the system, the A/D interface also needs to adhere to the low-power
low-voltage constraint. The trend of increasing integration level for integrated circuits
has forced the ADC interface to reside on the same silicon with large DSP and digital
circuits. Therefore, an ADC operating at the same voltage with the digital circuit is
desirable.
Among many types of CMOS ADC architectures, a pipelined architecture can
achieve good high input frequency dynamic performances and as a high throughput as
the flash ADC due to a S/H circuit in each stage of the pipeline ADC for concurrent
processing. In this thesis, both fundamental and practical limitations to the supply
voltage in CMOS ADCs are examined, and techniques to allow low voltage operation
of the pipelined architecture are described.
Present-day CMOS process is making the transition from 0.25μm, and 0.18μm
to 0.13μm. Digital circuits can reduce the power supply voltage as the process
advances, but for analog circuits, however, it is a great challenge to design the low
voltage circuits for a circuit designer. As far, the power supply of the ADC is from
1.5V to 3.0V. In this research, it is expected to use the battery as the power supply for
an ADC which is under 1.0V.
In this research, a 10-bit 5MS/s pipelined A/D converter with a 1.0 V voltage
supply has been designed and implemented with standard TSMC 0.25μm CMOS
1P5M process with NMOS and PMOS threshold voltages of 0.5V and 0.6V,
respectively. For realizing a pipelined ADC with low supply voltage, an innovative
circuit for multiplying digital-to-analog converter (MDAC) is accomplished with the
switched opamp technique without any multiplied voltage circuit or low-threshold
process. It also presents a reliable new low-voltage input sampling circuit as the S/H
of a pipelined ADC. Due to no problems of existing reliability, the proposed
low-voltage ADC is very suitable for the future advanced CMOS technology and
provides a great help for system integration.



Chapter 1 Introduction ……………………………………… 1
1.1 Motivation and Goal …………………………………………………… 1
1.2 Thesis Organization …………………………………………………… 3
Chapter 2 Fundamentals of Pipelined ADC ………………… 5
2.1 Introduction …………………………………………………………… 5
2.2 ADC Performance Metrics …………………………………………… 5
2.2.1 Resolution ……………………………………………………… 6
2.2.2 Signal to Noise Ratio …………………………………………… 6
2.2.3 Signal to Noise + Distortion Ratio ……………………………… 7
2.2.4 Dynamic Range ………………………………………………… 8
2.2.5 Nonlinearity ……………………………………………………… 9
2.3 Review of ADC Architecture ………………………………………… 10
2.3.1 Flash ADC ……………………………………………………… 11
2.3.2 Two Step Flash ADC …………………………………………… 12
2.3.3 Pipelined ADC …………………………………………………… 13
2.3.4 Cyclic ADC ……………………………………………………… 14
2.4 Key Building Blocks of Pipelined ADC ……………………………… 14
2.5 Digital Error Correction Technique …………………………………… 17
2.5.1 1.5-Bit / Stage Architecture ……………………………………… 18
2.6 Stage Accuracy Requirements ………………………………………… 20
2.7 Behavioral Model of Pipelined ADC ………………………………… 22
2.8 Summary ……………………………………………………………… 28
Table of Contents
VI
Chapter 3 The Design of Low-Voltage Pipelined ADC ……… 29
3.1 Introduction …………………………………………………………… 29
3.2 Trends Toward of Low-Power Low-Voltage IC ……………………… 29
3.3 Switched-Capacitor Techniques ……………………………………… 30
3.4 Low-Voltage Switched-Capacitor Techniques ………………………… 32
3.4.1 Voltage Multiplier ……………………………………………… 34
3.4.2 Clock Bootstrapped Switch ……………………………………… 35
3.4.3 Low-Threshold Voltage Process ………………………………… 36
3.4.4 Switched Opamp ………………………………………………… 36
3.5 Low-Voltage Multiplying Digital-to-Analog Converter ……………… 37
3.5.1 Conventional MDAC …………………………………………… 37
3.5.2 Low-Voltage MDAC …………………………………………… 38
3.6 Low-Voltage Input Sampling Circuit ………………………………… 44
3.7 Summary ……………………………………………………………… 47
Chapter 4 The Implementation of Low-Voltage Pipelined ADC … 49
4.1 Introduction …………………………………………………………… 49
4.2 Switched Opamp and Common Mode Feedback……………………… 49
4.2.1 Low-Voltage Switched Opamp ………………………………… 50
4.2.2 Low-Voltage Dynamic Common Mode Feedback Circuitry …… 53
4.2.3 Simulation Results of Switched Opamp ………………………… 55
4.3 Low-Voltage Comparator ……………………………………………… 58
4.4 Implementation of Bootstrapped switch ……………………………… 62
4.5 Clock Generator and Digital Circuitry ………………………………… 63
4.6 On-Chip Buffer ………………………………………………………… 65
4.7 The Simulated Results of Low-Voltage Pipelined ADC ……………… 66
4.8 Layout and Floor Plan ………………………………………………… 70
4.9 Summary ……………………………………………………………… 72
Chapter 5 Test Setup and Experimental Results …………… 73
5.1 Introduction …………………………………………………………… 73
5.2 Test Setup ……………………………………………………………… 73
5.2.1 Input Signal Source and Input Termination Circuit …………… 74
5.2.2 Power Supply and Ground ……………………………………… 75
Table of Contents
VII
5.2.3 Reference Voltage Generator …………………………………… 76
5.2.4 Clock Generator ………………………………………………… 77
5.3 Experimental Results ………………………………………………… 78
5.4 Summary ……………………………………………………………… 82
Chapter 6 Conclusions ……………………………………… 87
6.1 Conclusions …………………………………………………………… 87
6.2 Recommendations for Future Works ………………………………… 87

helianalog

怎么你给的第2个链接是讲PLL的？

xinlianxin

看上去还可以！

hnwulei

tttttttttttttttttttttt

adamsnet

正需要 感謝!!!

tuza2000

SWITCH OPAMP的

yuqiumax

回复 1# hi_china59

國立台灣大學電機工程學研究所碩士論文
指導教授：劉 深 淵 博士
一伏十位元CMOS
導管式類比數位轉換器
A 1.0-V, 10-Bit CMOS
Pipelined Analog-to-Digital Converter
研 究 生：鄭 光 偉 撰
中華民國九十一年六月

robberxiong

A nice paper. Thanks a lot.

brav

good job.......

sasso

good job