DDR verilog RTL

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File/Directory    Description
=============================================================================
\doc    DDR SDRAM reference design documentation
\model    Contains the verilog SDRAM model
\route    Contains the Quartus 2000.05 project files a routed controller design
\simulation   Contains the verilog testbench, modelsim project file, and library
\source    Contains the verilog source files for the DDR SDRAM reference design
\synthesis\synplicity  Contains all synplicity project files associated with synthesizing the reference design
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2011-10-23 23:10 上传

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