DFT新手求救：关于mentor的EDT，求帮助

shaoqingtju

在使用EDT压缩 scan chain时，采用了testkompress 生成ＥＤＴｉｐ和综合，在生成test pattern时，出现了error，Error: Scan chain chain1 blocked at gate /Scaler_top_edt_i/Scaler_top_edt_compactor_i (35522) after tracing 0 cells. (T3-1)
以下是运行的log，求达人解答：
/home/shaoqingtju/DFT/mgc_home.ixe/bin/testkompress edt_out/VFC_edt_top_gate.v -verilog -library lib.atpg -dofile VFC_pt_gen.do -logfile results/VFC_pt_gen.log -replace -nogui
//  TestKompress  v8.2007_2.10    Wed May 23 01:19:16 GMT 2007
//                Copyright 2001-2007 Mentor Graphics Corporation
//
//                           All Rights Reserved.
//
//    THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH
//  IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS
//                        SUBJECT TO LICENSE TERMS.
//
//  This product is covered by one or more of the following U.S. patents:
//    5,991,909; 6,327,687; 6,353,842; 6,539,409; 6,543,020; 6,557,129; 6,874,109.
//                         Foreign patents pending.
//
//  Mentor Graphics software executing under x86 Linux.
//  32 bit version
//  Host: localhost.localdomain (1 x 3.2 GHz, 1011 MB RAM, 1983 MB Swap)
//
//  Compiling library  ...
//  Reading DFT Library file lib.atpg
//  Finished reading file lib.atpg
//  Reading Verilog Netlist ...
//  Reading Verilog file edt_out/VFC_edt_top_gate.v
//  Finished reading file edt_out/VFC_edt_top_gate.v
//  Warning: Following modules are undefined:
//      GTECH_NOT
//      GTECH_BUF
//      GTECH_AND2
//      GTECH_OR2
//      SELECT_OP
//      **SEQGEN**
//      GTECH_XOR2
//  Use "add black box -auto" to treat these as black boxes
//  Warning: 591 cases: Unused net in DFT library model
//  Warning: 138 cases: Undriven net in netlist module
//  Warning: 106 cases: Primary input driven by another signal
//  Warning: 389 cases: Net in netlist not connected
//  Warning: 21 cases: Undefined module pin assumed to be output
//  Warning: 7 cases: Undefined module pin assumed to be input
//  Note: Invoke with '-load_warnings' to see detailed library and netlist load warnings
//  command: add black box -auto
//  command: dofile edt_out/VFC_edt.dofile
//  command: set edt instances -edt_logic_top Scaler_top_edt_i
//  Found edt_logic_top at path: "/Scaler_top_edt_i".
//  command: set edt instances -decompressor  Scaler_top_edt_decompressor_i
//  Found decompressor at path: "/Scaler_top_edt_i/Scaler_top_edt_decompressor_i".
//  command: set edt instances -compactor     Scaler_top_edt_compactor_i
//  Found compactor at path: "/Scaler_top_edt_i/Scaler_top_edt_compactor_i".
//  command: add scan groups grp1 edt_out/VFC_edt.testproc
//  command: add scan chains -internal chain1 grp1 /Scaler_top_i/Data_in[0] /Scaler_top_i/R_out[0]
//  command: add scan chains -internal chain2 grp1 /Scaler_top_i/Data_in[1] /Scaler_top_i/R_out[1]
//  command: add scan chains -internal chain3 grp1 /Scaler_top_i/Data_in[2] /Scaler_top_i/R_out[2]
//  command: add scan chains -internal chain4 grp1 /Scaler_top_i/Data_in[3] /Scaler_top_i/R_out[3]
//  command: add scan chains -internal chain5 grp1 /Scaler_top_i/Data_in[4] /Scaler_top_i/R_out[4]
//  command: add scan chains -internal chain6 grp1 /Scaler_top_i/Data_in[5] /Scaler_top_i/R_out[5]
//  command: add scan chains -internal chain7 grp1 /Scaler_top_i/Data_in[6] /Scaler_top_i/R_out[6]
//  command: add scan chains -internal chain8 grp1 /Scaler_top_i/Data_in[7] /Scaler_top_i/R_out[7]
//  command: add scan chains -internal chain9 grp1 /Scaler_top_i/Data_in[8] /Scaler_top_i/G_out[0]
//  command: add scan chains -internal chain10 grp1 /Scaler_top_i/Data_in[9] /Scaler_top_i/G_out[1]
//  command: add scan chains -internal chain11 grp1 /Scaler_top_i/Data_in[10] /Scaler_top_i/G_out[2]
//  command: add scan chains -internal chain12 grp1 /Scaler_top_i/Data_in[11] /Scaler_top_i/G_out[3]
//  command: add scan chains -internal chain13 grp1 /Scaler_top_i/Data_in[12] /Scaler_top_i/G_out[4]
//  command: add scan chains -internal chain14 grp1 /Scaler_top_i/Data_in[13] /Scaler_top_i/G_out[5]
//  command: add scan chains -internal chain15 grp1 /Scaler_top_i/Data_in[14] /Scaler_top_i/G_out[6]
//  command: add scan chains -internal chain16 grp1 /Scaler_top_i/Data_in[15] /Scaler_top_i/G_out[7]
//  command: add clocks 0 RST
//  command: add clocks 0 VGA_IN_DATA_CLK
//  command: add clocks 0 Clk_most
//  command: add clocks 0 out_pix_clk
//  command: add clocks 0 Sysclk
//  command: add clocks 0 scan_set
//  command: add clocks 0 edt_clock
//  command: add pin constraints test_en C1
//  command: add pin constraints edt_clock C0
//  command: set edt -channels 4 -bypass_logic on -pipeline_logic_levels_in_compactor 2 -longest_chain_range 9 350 -ip_version 3 -decompressor_size 32 -injectors_per_channel 4 -scan_chains 16
//  command: set edt pins update Href
//  command: set edt pins scan_en scan_en
//  command: set edt pins bypass Vref
//  command: set edt pins input_channel  1 Data_in[16]
//  command: set edt pins output_channel 1 B_out[0]
//  command: set edt pins input_channel  2 Data_in[17]
//  command: set edt pins output_channel 2 B_out[1]
//  command: set edt pins input_channel  3 Data_in[18]
//  command: set edt pins output_channel 3 B_out[2]
//  command: set edt pins input_channel  4 Data_in[19]
//  command: set edt pins output_channel 4 B_out[3]
//  command: set pattern type -sequential 2
//  Settings : -RAM_sequential OFF
//             -SEQuential     2
//             -MULtiple_load  OFF
//             -CLOck_po       ON
//  command: set system mode atpg
//  Warning: Rule FN1 violation occurs 527 times
//  Warning: Rule FN2 violation occurs 48 times
//  Flattening process completed,  design_cells=30639  library_primitives=127947  blackbox_tie=3729  sim_gates=108756  PIs=55  POs=29  CPU time=0.48 sec.
//  ---------------------------------------------------------------------------
//  Begin circuit learning analyses.
//  ---------------------------------------------------------------------------
//  Equivalent gates=1650   classes=688   CPU time=0.20 sec.
//  Learned gate functions: #BUFs=75 #INVs=27 #XORs=1100 #MUXs=1094
//  Learned relationships: #EQ_MUXs=2
//  Learned tied gates: #TIED_ORs=2
//  Learning activity limit exceeded: static learning process was truncated.
//  Learning completed, implications=34217, tied_gates=3024, CPU time=0.12 sec.
//  20 wired_gates are modeled as WIRE gates.
//  ---------------------------------------------------------------------------
//  Begin scan chain identification process, memory elements = 5590.
//  ---------------------------------------------------------------------------
//  Reading group test procedure file edt_out/VFC_edt.testproc.
//  Simulating load/unload procedure in grp1 test procedure file.
//  Error: Scan chain chain1 blocked at gate /Scaler_top_edt_i/Scaler_top_edt_compactor_i (35522) after tracing 0 cells. (T3-1)
//  Error: Scan chain chain2 blocked at gate /Scaler_top_edt_i/Scaler_top_edt_compactor_i (35523) after tracing 0 cells. (T3-2)
//  Error: Scan chain chain3 blocked at gate /Scaler_top_edt_i/Scaler_top_edt_compactor_i (35524) after tracing 0 cells. (T3-3)
//  Error: Scan chain chain4 blocked at gate /Scaler_top_edt_i/Scaler_top_edt_compactor_i (35525) after tracing 0 cells. (T3-4)
//  Error: Scan chain chain5 blocked at gate /Scaler_top_edt_i/Scaler_top_edt_compactor_i (35526) after tracing 0 cells. (T3-5)
//  Error: Scan chain chain6 blocked at gate /Scaler_top_edt_i/Scaler_top_edt_compactor_i (35527) after tracing 0 cells. (T3-6)
//  Error: Scan chain chain7 blocked at gate /Scaler_top_edt_i/Scaler_top_edt_compactor_i (35528) after tracing 0 cells. (T3-7)
//  Error: Scan chain chain8 blocked at gate /Scaler_top_edt_i/Scaler_top_edt_compactor_i (35529) after tracing 0 cells. (T3-8)
//  Error: Scan chain chain9 blocked at gate /Scaler_top_edt_i/Scaler_top_edt_compactor_i (35530) after tracing 0 cells. (T3-9)
//  Error: Scan chain chain10 blocked at gate /Scaler_top_edt_i/Scaler_top_edt_compactor_i (35531) after tracing 0 cells. (T3-10)
//  Error: Scan chain chain11 blocked at gate /Scaler_top_edt_i/Scaler_top_edt_compactor_i (35532) after tracing 0 cells. (T3-11)
//  Error: Scan chain chain12 blocked at gate /Scaler_top_edt_i/Scaler_top_edt_compactor_i (35533) after tracing 0 cells. (T3-12)
//  Error: Scan chain chain13 blocked at gate /Scaler_top_edt_i/Scaler_top_edt_compactor_i (35534) after tracing 0 cells. (T3-13)
//  Error: Scan chain chain14 blocked at gate /Scaler_top_edt_i/Scaler_top_edt_compactor_i (35535) after tracing 0 cells. (T3-14)
//  Error: Scan chain chain15 blocked at gate /Scaler_top_edt_i/Scaler_top_edt_compactor_i (35536) after tracing 0 cells. (T3-15)
//  Error: Scan chain chain16 blocked at gate /Scaler_top_edt_i/Scaler_top_edt_compactor_i (35577) after tracing 0 cells. (T3-16)
//  Error: Rules checking unsuccessful, cannot exit SETUP mode.
//         'DOFile VFC_pt_gen.do' aborted at line 4
  
//  command: exit

fxcprince

你的TestKompress是破解版吗？

junqiang0223

看一下 你的clock有没有都控制住了。

gxlong

你检查一下你的testproc文件中的setup过程里有没有将复位信号定义为有效了，这样所有的scan cell都会固定为0了，我之前跑EDT时碰到过一次。

lyt8650

4楼说的很可能，我也碰到过