逐点半导体（上海）有限公司

jessie1

FPGA Engineer
Responsibilities:
1.FPGA design  verification. Porting ASIC code to FPGA platform, verify the whole design in FPGA system.  
2.Lead the whole FPGA verification flow, include specification, coding, simulation, physical implementation  board level

debugging.  
3.Organize  Coordinate the work of debug team.  
4.Capability of making rapidly scheme/method to trace issue.  
5.RTL module development to assist the verification on FPGA  

Requirement：  
1.MS in Electronic or Computer Science Engineering is required. Expert in FPGA operation theory.  
2.More than 3 years experience in design  verify on FPGA.  
3.Project experience in mapping large scale, multi-million gate ASIC to multiple FPGAs  
4.Architecture  design flow Expert in Verilog or VHDL. Familiar with FPGA EDA tools, such as Synplify, ISE, QuartusII Expert

in Xilinx product.  
5.Strong coding skills in Verilog/VHDL RTL.  
6.Strong system bring up skills.  
7.Experience in Chip  system test.  
8.Analyze the FPGA requirement, evaluate the resource   the chip type in the design phase.  
9.Familiar with SOC architecture  OCP/AHB/APB.  
10.Familiar with video system is preferable  
11.The cidate is required to use the logic analyzer  oscillator to debug in FPGA Design.  
12.Outsting written  verbal communication skills in English
13. Familiar with FPGA co-simulation is preferable

jobic_cn@126.com

DSP Architecture Engineer
Job Description:
1. Response for design architecture of video/image processing chip /or video/image processing IP based on understing of video

processing algorithm  background knowledge of IC design  verification. Architecture engineers not only design architecture,

but also need cooperate with algorithm designers, IC designers  verification engineers.
2. Architecture design work includes mapping algorithm solution into hardware solution from following aspects:
a) Function partition of algorithm solution
b) Design Interface  interface’s protocol design between IP block or sub-block
c) Control mechanism define, calculation logic evaluation, storage size  bwidth evaluation based on cost, throughput,
3. Architecture designer is response for consider design’s cost which include die size, power consumption, rtl design  

verification effort.
4. Architecture designer is response for give valuable feedback to algorithm designers to optimize their algorithm from

cost/performance’s view
5. Architecture designer is response for support  accelerate IC implementation  verification by proper architecture partition  

modeling

Requirements
1. 2 - 3 (4 - 5 for senior) years experience in IC industry

2. IC design experience
a) RTL coding  debugging skill
b) Familiar with IC develop tools, such as ModelSim, Debussy

3. Architecture design  implementation experience of some of following aspects
a) calculation pipeline design
b) SRAM control
c) Typical bus protocol, OCP,
d) Familiar with DMA, DDR related topics

4. Video processing chip experience one of following aspects is nice to have:
a) Familiar with image processing or video processing algorithm  solution
b) Familiar with video compression stard, such as: MPEG, H.264

jobic_cn@126.com

Sr. IC Engineer
1.This cidate should have video-processing background  should be interesting in R&D on Video related technologies. Be able to

debug  work with SW on AFE/VDC issues reported from customers.
2. IC/FPGA background. Be interesting in developing  improving New IP  try to detailed underst it.
3.  With at least 5-years IP/Product R&D experience.

Job Description
RTL coding, new logic design, simulation, synthesis,  debug on the FPGA platform.
Work closely with algorithm engineer to develop/debug new IP/product.
Work closely with system/SW engineer to verificate/validate new IP/product on FPGA/System platform.
Deliver design/verification/application documents.  
Qualification  Experience
-Very familiar with the Verilog HDL language
-Create the RTL architecture for the algorithm
-Very familiar with C  C++
-Familiar with FPGA tool, ModelSim,  Synplify.
-Familiar with the flow of the IC design.

Requirements:
- Bachelor/Master degree in electronic/computer engineering
- Demonstrated abilities in working independently
- Strong communication skills
jobic_cn@126.com

Sr./ DFT Engineer
Required:  
1. Chip integration  full chip synthesis.   
2. Underst timing constraints  timing sign off at chip level.  
3. Familiar with DFT, including scan ion, ATPG generation, MBIST ion  functional test pattern generation.  
4. Can work with BE team, analog team  third party to drive full chip P&R  timing closure.
5. Familiar with synthesis tool as Magma, DC, Timing sign off tool as PT, simulation tool such as Modelsim or VCS.  
6.  3 years + work experience.  

Plus:
1. Design  verification background.
2. ATE Testing background.

IC人才网原链：http://www.jobic.cn/Html/JobDetails/11899.html
10月份注册简历赢ipad:http://www.jobic.cn/Resume/Register.aspx
邮箱：jobic_cn@126.com
电话：0755-26490606

evistera

都要工作经验，这让不让应届生活啊，

jessie1

呵呵～～～你也可以进www.jobic.cn IC人才里看看，还有很多公司不要工作经验的。希望对您有帮助。

晒太阳

好公司啊，不过俺在苏州，去不了啊

jessie1

这个没有关系啊～～～jobic.cn 上面还是有很多苏州的企业啊～～～

jessie1

大家多多给力啊～～～

jessie1

给力～～～～～

jessie1

大家一定要多多给力啊

helenhappy

好像还是外资企业，不过要求挺高的。有点够不到啊～～～

helenhappy

还是想看看。