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Optimized Layout on ESD Protection Diode with Low Parasitic Capacitance
Chih-Ting Yeh1,2 and Ming-Dou Ker2,3
1Circuit Design Department, Design Automation Technology Division,
Information and Communications Research Laboratories, Industrial Technology Research Institute, Hsinchu, Taiwan.
2 Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan.
Abstract
The diode operated in forward-biased condition has been
widely used as an effective on-chip electrostatic discharge
(ESD) protection device at GHz RF and high-speed I/O pads
in CMOS integrated circuits (ICs) due to the small parasitic
loading effect and high ESD robustness. Based on waffle
layout style, two modified layout styles have been proposed,
which are called as multi-waffle and multi-waffle-hollow
layout styles. Experimental results in a 90-nm CMOS process
have confirmed that the figures of merit (FOMs) of ESD
protection diodes with new proposed layout styles can be
successfully improved. |
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发表于 2011-10-5 21:24:29
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