2011--Layout Styles to Improve CDM ESD of 65nm

semico_ljj

Layout Styles to Improve CDM ESD Robustness
of Integrated Circuits in 65-nm CMOS Process

Ming-Dou Ker1,2, Chun-Yu Lin1, and Tang-Long Chang1
1 Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan.
2 Department of Electronic Engineering, I-Shou University, Kaohsiung, Taiwan

Abstract – Due to the thinner gate oxide in the nanoscale CMOS
technology and the larger chip size in the system-on-chip (SoC) IC
products, the charged-device-model (CDM) electrostatic discharge
(ESD) has become the major ESD events to cause failures during IC
manufacturing procedures. The effective ESD protection design
against CDM ESD stresses should be implemented into the chip with
layout optimization to improve its ESD robustness. In this work, the
impacts of different layout styles of MOS devices on CDM ESD
robustness were investigated in a 65-nm CMOS process. The
experimental results can provide useful information to optimize the
layout of integrated circuits against CDM ESD events.

semico_ljj

best...

mtwumtwu

good reference for ESD layout

tingyc

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jsp0520

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Jason_ke

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mmmqqqjjj

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pingdandan

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microcat

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dante5323

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