2011－Capacitor-Less of Power-Rail ESD Clamp－MD Ker

semico_ljj

Capacitor-Less Design of Power-Rail ESD Clamp
Circuit With Adjustable Holding Voltage for On-Chip
ESD Protection

Chih-Ting Yeh and Ming-Dou Ker, Fellow, IEEE

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 11, NOVEMBER 2010

Index Terms—Big field-effect transistor (BigFET), electrostatic
discharge (ESD), holding voltage, power-rail ESD clamp circuit.

semico_ljj

best。。。

Abstract—The RC-based power-rail ESD clamp circuit with the
n-channel metal-oxide-semiconductor (NMOS) transistor drawn
in the layout style of big field-effect transistor (BigFET) has been
utilized to effectively enhance the ESD robustness of CMOS ICs.
In this work, a new ESD-transient detection circuit without using
the capacitor has been proposed and verified in a 65 nm 1.2 V
CMOS process. The layout area of the new ESD-transient detection
circuit can be greatly reduced by more than 54%, as compared
to the traditional RC-based ESD-transient detection circuit
realized with capacitor. From the experimental results, the new
proposed ESD-transient detection circuit with adjustable holding
voltage can achieve long enough turn-on duration under the ESD
stress condition, as well as better immunity against mistrigger and
transient-induced latch-on event under the fast power-on and transient
noise conditions.

tingyc

Good!

mingyulane

3QQQQQQQQQQQQ

lupo

个人感觉挺好

hw9601

Thanks a lot!!!!

xuleiwx

一篇论文，11页

happywith123us

3kyyyyyyyyyyyyyyyyyyyy

dylan_uestc

MD Ker,paper  for ESD on JSSC

Claire90

thanks