招聘Senior / Design verification Engineer-Shanghai

judy102

Senior / Design verification Engineer

Job Description and Responsibilities:
-Responsible for logic verification of memory products.
-Generate test plan and test vectors according to product spec.
-Generate Random engineer and coverage group by system verilog/script.
-Responsible for the developments of specified flash memory products or embedded flash IPs.
-Support the design kits include verilog model synthesis lib generation and of embedded flash IPs.

Key Competency Requirements:
-Basic IC design and verification methodology.
-Experience in memory macro modeling, verilog simulation or synthesis lib generation
-Knowledge of non-volatile memory circuits and architecture is a definite advantage.
-Tools used may include Verilog, HSPICE/HSIM, Cadence Design Entry, Synopsys synthesis tools, P&R tools, IC layout tools, or other equivalent tools

Education and Experience Required:
-Bachelor degree or above in EE
-3+years logic verification experience is preferred.
-Preferred- Memory (especial Flash memory) knowledge.
-Advanced verification methodology knowledge is preferred.

想了解更多关于职位或公司信息可以联系judy
Tel: 13764174419; 021-61023600*858
Email:digital2@kthr.com
MSN:lily.12120@hotmail.com