FPGA-Based Prototyping Methodology Manual

jiancongwoo

先占个坑，回复到20人，立马发上来。

etopyes8

我要啊。。。。

pontiff

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billwaston

谢谢分享

huanguestc002

kankan z shuo

jiancongwoo

哈哈，不需要发了。

y3rike

HAH

不能卖关子啊
这个年代

mscyc0909

CHAPTER 1 Introduction: the challenge of system verification................. 1
1.1. Moore was right!..................................................................................... 1
1.1.1. SoC: A definition . . . for this book at least............................ 1
1.2. The economics of SoC design ................................................................. 2
1.2.1. Case study: a typical SoC development project ..................... 4
1.3. Virtual platforms: prototyping without hardware..................................... 6
1.3.1. SDK: a very common prototyping environment .................... 7
1.3.2. FPGA: prototyping in silicon . . . but pre-silicon................... 8
1.3.3. Emulators: prototyping or verification?................................. 9
1.3.4. First silicon as a prototype platform.................................... 10
1.4. Prototyping use models ......................................................................... 10
1.4.1. Prototyping for architecture exploration.............................. 11
1.4.2. Prototyping for software development ................................ 11
1.4.3. Prototyping for verification................................................. 12
1.5. User priorities in prototyping................................................................. 13
1.6. Chip design trends................................................................................. 15
1.6.1. Miniaturization towards smaller technology nodes.............. 15
1.6.2. Decrease in overall design starts ......................................... 16
1.6.3. Increased programmability and software............................. 17
1.6.4. Intellectual property block reuse ......................................... 19
1.6.5. Application specificity and mixed-signal design ................. 21
1.6.6. Multicore architectures and low power ............................... 22
1.7. Summary............................................................................................... 23
CHAPTER 2 What can FPGA-based prototyping do for us? ................... 25
2.1. FPGA-based prototyping for different aims........................................... 25
2.1.1. High performance and accuracy.......................................... 26
2.1.2. Real-time dataflow ............................................................. 27
2.1.3. Hardware-software integration............................................ 28
2.1.4. Modeling an SoC for software development ....................... 28
2.1.5. Example prototype usage for software validation................ 30
2.2. Interfacing benefit: test real-world data effects ...................................... 33
2.2.1. Example: prototype immersion in real-world data............... 34
2.3. Benefits for feasibility lab experiments ................................................. 35
2.4. Prototype usage out of the lab ............................................................... 36
2.4.1. Example: A prototype in the real world............................... 36
2.5. What can’t FPGA-based prototyping do for us? .................................... 38
2.5.1. An FPGA-based prototype is not a simulator ...................... 38
2.5.2. An FPGA-based prototype is not ESL................................. 39
2.5.3. Continuity is the key........................................................... 39
2.6. Summary: So why use FPGA-based prototyping? ................................. 40
CHAPTER 3 FPGA technology today: chips and tools ............................. 41
3.1. FPGA device technology today............................................................. 41
3.1.1. The Virtex®-6 family: an example of latest FPGAs ............. 42
3.1.2. FPGA logic blocks.............................................................. 43
3.1.3. FPGA memory: LUT memory and block memory .............. 46
3.1.4. FPGA DSP resources.......................................................... 47
3.1.5. FPGA clocking resources.................................................... 49
3.1.6. FPGA input and output ....................................................... 51
3.1.7. Gigabit transceivers ............................................................ 53
3.1.8. Built-in IP (Ethernet, PCI Express®, CPU etc.) ................... 54
3.1.9. System monitor................................................................... 55
3.1.10. Summary of all FPGA resource types ............................... 56
3.2. FPGA–based Prototyping process overview.......................................... 57
3.3. Implementation tools needed during prototyping................................... 59
3.3.1. Synthesis tools .................................................................... 60
3.3.2. Mapping SoC design elements into FPGA .......................... 61
3.3.3. Synthesis and the three “laws” of prototyping..................... 63
3.3.4. Gated clock mapping .......................................................... 65
3.4. Design partitioning flows ...................................................................... 66
3.4.1. Pre-synthesis partitioning flow............................................ 67
3.4.2. Post-synthesis partitioning flow.......................................... 68
3.4.3. Alternative netlist-based partitioning flow .......................... 70
3.4.4. Partitioning tool example: Certify®.................................... 72
3.5. FPGA back-end (place & route) flow.................................................... 73
3.5.1. Controlling the back-end..................................................... 75
3.5.2. Additional back-end tools ................................................... 77
3.6. Debugging tools .................................................................................... 77
3.6.1. Design instrumentation for probing and tracing................... 78
3.6.2. Real-time signal probing: test points ................................... 78
3.6.3. Real-time signal probing: non-embedded ............................ 80
3.6.4. Non real-time signal tracing................................................ 81
3.6.5. Signal tracing at netlist level ............................................... 82
3.6.6. Signal tracing at RTL.......................................................... 85
3.6.7. Summarizing debugging tool options .................................. 89
3.7. Summary............................................................................................... 90
CHAPTER 4 Getting started ...................................................................... 91
4.1. A getting-started checklist ..................................................................... 91
4.2. Estimating the required resources: FPGAs............................................. 92
4.2.1. How mature does the SoC design need to be? ..................... 93
4.2.2. How much of the design should be included?...................... 94
4.2.3. Design blocks that map outside of the FPGA...................... 95
4.2.4. How big is an FPGA? ......................................................... 97
4.2.5. How big is the whole SoC design in FPGA terms?.............. 99
4.2.6. FPGA resource estimation ................................................ 100
4.2.7. How fast will the prototype run?....................................... 102
4.3. How many FPGAs can be used in one prototype? ............................... 104
4.4. Estimating required resources.............................................................. 106
4.5. How long will it take to process the design? ........................................ 106
4.5.1. Really, how long will it take to process the design? .......... 108
4.5.2. A note on partitioning runtime .......................................... 109
4.6. How much work will it be? ................................................................. 109
4.6.1. Initial implementation effort ............................................. 110
4.6.2. Subsequent implementation effort..................................... 111
4.6.3. A note on engineering resources ....................................... 111
4.7. FPGA platform ................................................................................... 112
4.8. Summary............................................................................................. 113
CHAPTER 5 Which platform? (1) build-your-own................................. 115
5.1. What is the best shape for the platform? .............................................. 115
5.1.1. Size and form factor.......................................................... 115
5.1.2. Modularity........................................................................ 117
5.1.3. Interconnect...................................................................... 119
5.1.4. Flexibility ......................................................................... 121
5.2. Testability ........................................................................................... 122
5.3. On-board clock resources .................................................................... 123
5.3.1. Matching clock delays on and off board............................ 124
5.3.2. Phase-locked loops (PLL)................................................. 125
5.3.3. System clock generation ................................................... 126
5.4. Clock control and configuration .......................................................... 128
5.5. On-board Voltage Domains................................................................. 128
5.6. Power supply and distribution ............................................................. 129
5.6.1. Board-level power distribution.......................................... 131
5.6.2. Power distribution physical design considerations............. 132
5.7. System reliability management............................................................ 133
5.7.1. Power supply monitoring .................................................. 133
5.7.2. Temperature monitoring and management ........................ 134
5.7.3. FPGA cooling................................................................... 136
5.8. FPGA configuration............................................................................ 137
5.9. Signal integrity.................................................................................... 138
5.10. Global start-up and reset.................................................................... 139
5.11. Robustness ........................................................................................ 139
5.12. Adopting a standard in-house platform.............................................. 140

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CHAPTER 6 Which platform? (2) ready-made ....................................... 143
6.1. What do you need the board to do?...................................................... 143
6.2. Choosing the board(s) to meet your goals............................................ 144
6.3. Flexibility: modularity......................................................................... 146
6.4. Flexibility: interconnect ...................................................................... 147
6.5. What is the ideal interconnect topology? ............................................. 150
6.6. Speed: the effect of interconnect delay ................................................ 153
6.6.1. How important is interconnect flight time? ....................... 156
6.7. Speed: quality of design and layout ..................................................... 157
6.8. On-board support for signal multiplexing ............................................ 158
6.9. Cost and robustness............................................................................. 159
6.9.1. Supply of FPGAs governs delivery of boards.................... 160
6.10. Capacity............................................................................................ 160
6.11. Summary........................................................................................... 162
CHAPTER 7 Getting the design ready for the prototype ........................ 165
7.1. Why “get the design ready to prototype?” ........................................... 165
7.1.1. RTL modifications for prototyping ................................... 166
7.2. Adapting the design’s top level ........................................................... 167
7.2.1. Handling the IO pads ........................................................ 168
7.2.2. Handling top-level chip support elements ......................... 168
7.3. Clock gating........................................................................................ 170
7.3.1. Problems of clock gating in FPGA.................................... 171
7.3.2. Converting gated clocks.................................................... 172
7.4. Automatic gated-clock conversion....................................................... 174
7.4.1. Handling non-convertible gating logic .............................. 176
7.4.2. Clock gating summary...................................................... 179
7.5. Selecting a subset of the design for prototyping................................... 180
7.5.1. SoC block removal and its effect....................................... 180
7.5.2. SoC element tie-off with stubs .......................................... 183
7.5.3. Minimizing and localizing RTL changes........................... 184
7.5.4. SoC element replacement with equivalent RTL................. 186
7.5.5. SoC element replacement by inference ............................. 189
7.5.6. SoC element replacement by instantiation......................... 191
7.5.7. Controlling inference using directives............................... 193
7.6. Handling RAMs .................................................................................. 194
7.7. Handling instantiated SoC RAM in FPGA .......................................... 195
7.7.1. Note: RAMs in Virtex®-6 FPGAs ..................................... 195
7.7.2. Using memory wrappers ................................................... 197
7.7.3. Advanced self-checking wrappers..................................... 204
7.8. Implementing more complex RAMs.................................................... 207
7.8.1. Example: implementing multiport RAMs.......................... 207
7.8.2. Example: bit-enabled RAMs............................................. 209
7.8.3. NOTE: using BlockRAM as ROMs .................................. 212
7.9. Design implementation: synthesis ....................................................... 212
7.9.1. Note: using existing constraints for the SoC design........... 213
7.9.2. Tuning constraints ............................................................ 215
7.10. Prototyping power-saving features .................................................... 215
7.11. Design implementation: place & route............................................... 216
7.12. Revision control during prototyping .................................................. 218
7.13. Summary........................................................................................... 219
CHAPTER 8 Partitioning and reconnecting ............................................ 221
8.1. Do we always need to partition across FPGAs? ................................... 221
8.1.1. Do we always need EDA partitioning tools? ..................... 222
8.2. General partitioning overview ............................................................. 222
8.2.1. Recommended approach to partitioning ............................ 223
8.2.2. Describing board resources to the partitioner .................... 224
8.2.3. Estimate area of each sub-block ........................................ 225
8.2.4. Assign SoC top-level IO ................................................... 226
8.2.5. Assign highly connected blocks ........................................ 227
8.2.6. Assign largest blocks ........................................................ 229
8.2.7. Assign remaining blocks................................................... 231
8.2.8. Replicate blocks to save IO............................................... 231
8.2.9. Multiplex excessive FPGA interconnect ........................... 234
8.2.10. Assign traces................................................................... 234
8.2.11. Iterate partitioning to improve speed and fit .................... 237
8.3. Automated partitioning........................................................................ 239
8.4. Improving prototype performance ....................................................... 240
8.4.1. Time budgeting at sequential boundaries .......................... 241
8.4.2. Time budgeting at combinatorial boundaries..................... 242
8.5. Design synchronization across multiple FPGAs .................................. 244
8.5.1. Multi-FPGA clock synchronization................................... 244
8.5.2. Multi-FPGA reset synchronization.................................... 247
8.5.3. Multi FPGA start-up synchronization ............................... 250
8.6. More about multiplexing ..................................................................... 251
8.6.1. What do we need for inter-FPGA multiplexing? ............... 251
8.7. Multiplexing schemes ......................................................................... 253
8.7.1. Schemes based on multiplexer .......................................... 253
8.7.2. Note: qualification criteria for multiplexing nets ............... 254
8.7.3. Schemes based on shift-registers....................................... 255
8.7.4. Worked example of multiplexing...................................... 256
8.7.5. Scheme based on LVDS and IOSERDES.......................... 262
8.7.6. Which multiplexing scheme is best for our design?........... 264
8.8. Timing constraints for multiplexing schemes ...................................... 265
8.9. Partitioning and reconnection: summary.............................................. 266
CHAPTER 9 Design-for-Prototyping ....................................................... 267
9.1. What is Design-for-Prototyping? ......................................................... 267
9.1.1. What’s good for FPGA is usually good for SoC................ 268
9.2. Procedural guidelines .......................................................................... 268
9.2.1. Integrate RTL team and prototypers.................................. 269
9.2.2. Define list of deliverables for prototyping team ................ 270
9.2.3. Prototypers work with software team................................ 272
9.3. Integrate the prototype with the verification plan................................. 272
9.3.2. Documentation well and use revision control.................... 274
9.3.3. Adopt company-wide standard for hardware..................... 274
9.3.4. Include Design-for-Prototyping in RTL standards............. 274
9.4. Design guidelines................................................................................ 275
9.4.1. Follow modular design principles ..................................... 277
9.4.2. Pre-empt RTL changes with ‘define and macros ............... 278
9.4.3. Avoid latches.................................................................... 279
9.4.4. Avoid long combinatorial paths ........................................ 279
9.4.5. Avoid combinatorial loops................................................ 280
9.4.6. Provide facility to override FFs with constants.................. 280
9.5. Guidelines for isolating target specificity ............................................ 281
9.5.1. Write pure RTL code........................................................ 281
9.5.2. Make source changes as low-impact as possible................ 281
9.5.3. Maintain memory compatibility........................................ 282
9.5.4. Isolation of RAM and other macros .................................. 282
9.5.5. Use only IP that has an FPGA version or test chip ............ 284
9.6. Clocking and architectural guidelines .................................................. 284
9.6.1. Keep clock logic in its own top-level block....................... 285
9.6.2. Simplify clock networks for FPGA................................... 285
9.6.3. Design synchronously....................................................... 286
9.6.4. Synchronize resets ............................................................ 286
9.6.5. Synchronize block boundaries........................................... 286
9.6.6. Think how the design might run if clocked slowly ............ 287
9.6.7. Enable bottom-up design flows ......................................... 287
9.7. Summary............................................................................................. 288

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CHAPTER 10 IP and high-speed interfaces............................................... 289
10.1. IP and prototyping ............................................................................. 289
10.2. IP in many forms............................................................................... 290
10.2.1. IP as RTL source code .................................................... 291
10.2.2. What if the RTL is not available?.................................... 291
10.2.3. IP as encrypted source code ............................................ 292
10.2.4. Encrypted FPGA netlists................................................. 293
10.2.5. Encrypted FPGA bitstreams............................................ 293
10.2.6. Test chips ....................................................................... 295
10.2.7. Extra FPGA pins needed to link to test chips................... 297
10.3. Soft IP............................................................................................... 298
10.3.1. Replacing instantiated soft IP.......................................... 301
10.3.2. Replacing inferred soft IP ............................................... 301
10.3.3. Replacing synthetic soft IP.............................................. 302
10.3.4. Other FPGA replacements for SoC soft IP ...................... 304
10.4. Peripheral IP ..................................................................................... 304
10.4.1. Use mode 1: prototype the IP itself ................................. 305
10.4.2. Use mode 2: prototype the IP as part of an SoC............... 306
10.4.3. Use mode 3: prototype IP for software validation............ 307
10.5. Use of external hard IP during prototyping ........................................ 308
10.6. Replacing IP or omitted structures with FPGA IP .............................. 308
10.6.1. External peripheral IP example: PCIe and SATA............ 309
10.6.2. Note: speed issues, min-speed......................................... 310
10.7. Summary........................................................................................... 311
CHAPTER 11 Bring up and debug: the prototype in the lab.................... 313
11.1. Bring-up and debug–two separate steps? ........................................... 313
11.2. Starting point: a fault-free board........................................................ 314
11.3. Running test designs.......................................................................... 316
11.3.1. Filter test design for multiple FPGAs .............................. 317
11.3.2. Building a library of bring-up test designs....................... 319
11.4. Ready to go on board?....................................................................... 320
11.4.1. Reuse the SoC verification environment ......................... 321
11.4.2. Common FPGA implementation issues........................... 321
11.4.3. Timing violations............................................................ 322
11.4.4. Improper inter-FPGA connectivity.................................. 325
11.4.5. Improper connectivity to the outside world ..................... 327
11.4.6. Incorrect FPGA IO pad configuration ............................. 328
11.5. Introducing the design onto the board................................................ 331
11.5.1. Note: incorrect startup state for multiple FPGAs ............. 332
11.6. Debugging on-board issues ............................................................... 333
11.6.1. Sources of faults ............................................................. 333
11.6.2. Logical design issues ...................................................... 334
11.6.3. Logic debug visibility ..................................................... 335
11.6.4. Bus-based design access and instrumentation.................. 336
11.6.5. Benefits of a bus-based access system............................. 339
11.6.6. Custom debug using an embedded CPU.......................... 341
11.7. Note: use different techniques during debug ...................................... 342
11.8. Other general tips for debug .............................................................. 343
11.9. Quick turn-around after fixing bugs................................................... 346
11.9.1. Incremental synthesis flow.............................................. 347
11.9.2. Automation and parallel synthesis................................... 349
11.9.3. Incremental place & route flow....................................... 350
11.9.4. Combined incremental synthesis and P&R flow.............. 351
11.10. A bring-up and debug checklist ....................................................... 352
11.11. Summary......................................................................................... 353
CHAPTER 12 Breaking out of the lab: the prototype in the field............. 355
12.1. The uses and benefits of a portable prototype .................................... 355
12.2. Planning for portability ..................................................................... 357
12.2.1. Main board physical stiffness.......................................... 358
12.2.2. Daughter board mounting ............................................... 358
12.2.3. Board mounting holes ..................................................... 358
12.2.4. Main board connectors.................................................... 359
12.2.5. Enclosure........................................................................ 359
12.2.6. Cooling ........................................................................... 360
12.2.7. Look and feel.................................................................. 361
12.2.8. Summary ........................................................................ 362
CHAPTER 13 Prototyping + Verification = The Best of Both Worlds ..... 363
13.1. System prototypes ............................................................................. 363
13.2. Required effort .................................................................................. 364
13.3. Hybrid verification scenarios............................................................. 365
13.4. Verification interfaces ....................................................................... 365
13.4.1. Interfaces for co-simulation ............................................ 366
13.4.2. Interfaces for transaction-based verification.................... 368
13.4.3. TLMs and transactors ..................................................... 369
13.4.4. SCE-MI.......................................................................... 369
13.4.5. SCE-MI 2.0 implementation example ............................. 371
13.4.6. VMM HAL..................................................................... 373
13.4.7. Physical interfaces for co-verification ............................. 375
13.5. Comparing verification interface technologies................................... 375
13.6. Use models – more detail .................................................................. 377
13.6.1. Virtual platform re-using existing RTL ........................... 377
13.7. Virtual platform for software............................................................. 378
13.7.1. Virtual platform as a testbench........................................ 379
13.7.2. Virtual and physical IO (system IO)................................ 380
13.7.3. Virtual ICE..................................................................... 381
13.8. System partitioning ........................................................................... 383
13.9. Case study: USB OTG ...................................................................... 384
13.9.1. USB OTG System overview ........................................... 384
13.9.2. Integration use models .................................................... 385
13.9.3. Innovator and VCS ......................................................... 385
13.9.4. Innovator and CHIPit or HAPS....................................... 386
13.9.5. Virtual platform.............................................................. 387
CHAPTER 14 The future of prototyping ................................................... 391
14.1. If prediction were easy. . . ................................................................. 391
14.2. Application specificity ...................................................................... 391
14.3. Prototyping future: mobile wireless and consumer............................. 392
14.4. Prototyping future: networking.......................................................... 394
14.5. Prototyping future: automotive .......................................................... 397
14.6. Summary: software-driven hardware development ............................ 400
14.7. Future semiconductor trends.............................................................. 401
14.8. The FPGA’s future as a prototyping platform.................................... 402
14.9. Summary........................................................................................... 403
CHAPTER 15 Conclusions ......................................................................... 405
15.1. The FPMM approach to FPGA-based prototyping............................. 405
15.2. SoCs are larger than FPGAs .............................................................. 406
15.3. SoCs are faster than FPGAs .............................................................. 407
15.4. SoCs designs are FPGA-hostile ......................................................... 407
15.5. Design-for-Prototyping beats the three laws ...................................... 408
15.6. So, what did we learn? ...................................................................... 409
APPENDIX A: Worked Example: Texas Instruments………….....………...411
A1. Design background: packet processing sub-system.............................. 411
A2. Why does Texas Instruments do prototyping? ..................................... 412
A3. Testing the design using an FPGA-based prototype ............................. 413
A4. Implementation details ........................................................................ 415
A5. High-speed scenario ............................................................................ 416
A6. Low-speed scenario............................................................................. 417
A7. Interesting challenges .......................................................................... 418
A8. Summary of results ............................................................................. 421
APPENDIX B: Economics of making prototype boards…………………….421
B1. Prototyping hardware: should we make or buy?................................... 423
B2. Cost: what is the total cost of a prototyping board?.............................. 424
B3. Direct cost: personnel .......................................................................... 424
B4. Direct cost: equipment and expertise ................................................... 425
B5. Direct cost: material and components .................................................. 427
B6. Direct cost: yield and wastage ............................................................. 429
B7. Direct cost: support and documentation ............................................... 429
B8. Business cost: time .............................................................................. 430
B9. Business cost: risk ............................................................................... 433
B10. Business cost: opportunity................................................................. 435
B11. CCS worked example results ............................................................. 435
B12. Summary........................................................................................... 437