本帖最后由 sages 于 2011-9-11 12:39 编辑
回复 3# remnant
从仿真波形上明显看出,VCS报hold time violation的地方并不是我出现XXXX很多的地方,出现XXXX大概是在80000,所以就不是您说的报warning就出现XX的情况。按照你的要求,我在simulator的时候选项中已经加入了-no_notifier了,但是却有下面的warning。。。。
Warning: unknown flag: '-no_notifier' ignored
Chronologic VCS simulator copyright 1991-2008
Contains Synopsys proprietary information.
Compiler version A-2008.09; Runtime version A-2008.09; Sep 11 12:18 2011
Doing SDF annotation ...... Done
VCD+ Writer A-2008.09 Copyright 2005 Synopsys Inc.
File /.../inter.vpd is opened successfully.
testbench.v, 54 : #30 $stop;
"smic13g.v", 18775: Timing violation in testbench.TOP1.add1_ext_reg_reg_12_
$hold( posedge CK &&& (flag == 1'b1):16000, negedge D:16000, limit: 500 );
"smic13g.v", 18775: Timing violation in testbench.TOP1.add1_ext_reg_reg_13_
$hold( posedge CK &&& (flag == 1'b1):16000, negedge D:16000, limit: 500 );
"smic13g.v", 18775: Timing violation in testbench.TOP1.add1_ext_reg_reg_14_
$hold( posedge CK &&& (flag == 1'b1):16000, negedge D:16000, limit: 500 );
"smic13g.v", 18774: Timing violation in testbench.TOP1.acc1_reg1_reg_2_
$hold( posedge CK &&& (flag == 1'b1):26000, posedge D:26000, limit: 500 );
"smic13g.v", 18774: Timing violation in testbench.TOP1.add1_ext_reg_reg_9_
$hold( posedge CK &&& (flag == 1'b1):56000, posedge D:56000, limit: 500 );
正确的时序仿真图在做原型验证的时候应该如下:
求问这是怎么回事呢?
我的STA结果如上面已经给出了。 |