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急招
职位:DFT manager and Senior/staff DFT Engineer
地点:上海
感兴趣的兄弟姐妹可以联系:
QQ:1914346955
Mail:1914346955@qq.com
JD:
Senior / Staff ASIC DFT engineer (MCE ASIC)
Location: Shanghai
Qualifications:
1. BS (MS preferred) in microelectronics, electrical engineering or equivalent with 3+ years of DFT design experience, preferably with large SoC chips.
2. Handy experience on scan, mbist, boundary scan, ATPG and analog DFT, with Mentor/Synopsys/Syntest tools and RTL/gate simulation.
3. RTL design and STA experience is a strong plus.
4. ATE tester experience is a plus.
5. Must be able to communicate in both written and spoken English
6. Good team work spirit and communication skill.
Description:
Sr. / Staff ASIC DFT design engineer Focus on DFT design & debugging of leading-edge large SoC.
JD: DFT team manager (MCE ASIC)
Location: Shanghai
Qualifications:
1. BS (MS preferred) in microelectronics, electrical engineering or equivalent with 5+ years of DFT design experience, preferably with large SoC chips.
2. Handy experience on scan, mbist, boundary scan, ATPG and analog DFT, with Mentor/Synopsys/Syntest tools and RTL/gate simulation.
3. Good communication skill in a multi-national multi-team working environment. Experience with ATE tester and Production Engineer is a strong plus.
4. RTL design and STA experience is a strong plus.
6. Fluent in both written and spoken English
Description:
DFT team manager
Focus on leading the DFT team for DFT design & debugging of leading-edge large SoC, and work with Production Engineering team on large volume production.
其它职位继续招聘,参见:
http://bbs.eetop.cn/thread-302867-1-4.html |
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