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楼主 |
发表于 2011-8-12 09:52:50
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具体的报错信息是这样的,哪位大哥帮忙看看啊:
SYSERR:Unable to hdbBind for inst I0 in cell module inv,lib analogV3,view functional,configViewString $defult.
USRERR:Selected context view string'Spectre spice verilog behavioral functional hdl system verilognetlist cmos.sch cmos_sch veriloga ahdl' offers no suitable view for inst I0 referncing placed master mini_4k.not.symbol in cel Module in,lib analogv3,view functional,configviewstring $ default. Please check HDB configuration or library setup.
*Error* Failed to partition the design.
...unsuccessful.
*Error* Cannot create and partition the design.
*Error* Must fix design errors before netlisting.
...unsuccessful. "
我仿的是一个简单的电路,模拟的晶体管级与非门(I0)和一个verilog写的反向器,外加analoglib中的一些电压激励。 |
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