Techniques for High-Performance Digital Frequency Synthesis and Phase Control

hi_china59

Techniques for High-Performance Digital Frequency Synthesis and Phase Control
by
Chun-Ming Hsu
Bachelor of Science in Engineering
National Taiwan University, June 1997
Master of Science
National Taiwan University, June 1999
Submitted to the Department of Electrical Engineering and Computer
Science
in partial ful¯llment of the requirements for the degree of
Doctor of Philosophy in Electrical Engineering and Computer Science
at the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
September 2008

Contents
1 Introduction 21
1.1 Area of focus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.2 Proposed Digital Frequency Synthesis Technique . . . . . . . . . . . . 22
1.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.2.2 Quantization Noise Cancellation . . . . . . . . . . . . . . . . . 23
1.2.3 Digital-to-Analog Converter . . . . . . . . . . . . . . . . . . . 25
1.2.4 Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.2.5 Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.3 Proposed Digital Phase Control Technique . . . . . . . . . . . . . . . 27
1.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.3.2 Synthesizer-based Phase Shifter . . . . . . . . . . . . . . . . . 30
1.3.3 ¢§ Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.4 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.5 Overview of Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2 Proposed Techniques for Achieving a Low-Noise and Wide-Bandwidth
Digital PLL 35
2.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.2 Challenge of a Low-noise Wide-bandwidth Digital PLL . . . . . . . . 40
2.3 Review of the Gated Ring Oscillator TDC . . . . . . . . . . . . . . . 44
2.4 Review of the Previous Noise Cancellation Techniques in an Analog PLL 47
2.5 Proposed Digital Noise Cancellation Technique . . . . . . . . . . . . . 50
2.6 Proposed Digital ¢§ Fractional-N Synthesizer . . . . . . . . . . . . . 52
2.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3 Digital-to-Analog Converter for VCO Control 57
3.1 Passive Digital-to-Analog Converter . . . . . . . . . . . . . . . . . . . 58
3.1.1 DAC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.1.2 Design Considerations and Implementation Details . . . . . . 59
3.1.3 Settling Time Calculation . . . . . . . . . . . . . . . . . . . . 64
3.1.4 Noise Calculation . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.2 Hybrid VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.3 DCO Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

4 Asynchronous Divider 79
4.1 Asynchronous, Low-Jitter Divider . . . . . . . . . . . . . . . . . . . . 79
4.1.1 Divider Operation . . . . . . . . . . . . . . . . . . . . . . . . 81
4.1.2 Implementation Details . . . . . . . . . . . . . . . . . . . . . . 83
4.2 The TDC Unwrapping Function . . . . . . . . . . . . . . . . . . . . . 90
4.3 TDC O®set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

5 PLL System Design 95
5.1 System Design Using PLL Design Assistant . . . . . . . . . . . . . . 95
5.2 ¢§ Modulator Design . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5.3 PLL Type and Order . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5.4 Proposed Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5.5 Calculation of the Loop Filter Parameters . . . . . . . . . . . . . . . 105
5.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

6 Noise Analysis and Behavior Simulation 111
6.1 Noise Analysis of the Proposed Digital Synthesizer . . . . . . . . . . 111
6.1.1 PLL Noise Modeling . . . . . . . . . . . . . . . . . . . . . . . 111
6.1.2 Overall Phase Noise Calculation . . . . . . . . . . . . . . . . . 115
6.2 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.2.1 PLL Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.2.2 Reference Frequency . . . . . . . . . . . . . . . . . . . . . . . 123
6.2.3 Bandwidth of the Coarse-tuning DAC . . . . . . . . . . . . . . 124
6.2.4 Coarse-tuning VCO Gain . . . . . . . . . . . . . . . . . . . . . 125
6.3 Behavior Simulation with CppSim . . . . . . . . . . . . . . . . . . . . 126
6.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

7 Digital Synthesizer Measurement 133
7.1 Area and Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 133
7.2 VCO Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
7.3 Phase Noise and Spurs . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7.4 Locking Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
7.5 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
7.6 Improved phase noise at 20 MHz o®set . . . . . . . . . . . . . . . . . 151
7.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

8 Proposed Techniques for Digital Phase Control 153
8.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
8.2 Proposed DLL Architecture . . . . . . . . . . . . . . . . . . . . . . . 156
8.2.1 Synthesizer-based Phase Shifter . . . . . . . . . . . . . . . . . 156
8.2.2 ¢§ Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . 162
8.2.3 Bang-bang Detector . . . . . . . . . . . . . . . . . . . . . . . 167
8.3 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 168
8.4 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
8.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

9 Conclusion 175
9.1 Thesis Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
9.2 Future Research . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

学知11

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