A COMPENSATION-BASED OPTIMIZATION METHODOLOGY FOR GAIN-BOOSTED

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A COMPENSATION-BASED OPTIMIZATION METHODOLOGY FOR GAIN-BOOSTED

new4

good one

new4

Thanks for sharing

semico_ljj

A gain-boosted OPAMP design methodology is presented.
The methodology provides a systematic way of gain-boosted
OPAMP optimization in terms of AC response and settling
performance. The evolution of the major poles and zeros of
the gain-boosted OPAMP is studied, which reveals the rationale
behind our optimization effort. A sample OPAMP
was implemented in 0.6 µm CMOS technology. It achieves
a DC gain of 88dB, a bandwidth of 725MHz with 49◦ phase
margin and a 0.1% settling time of 4.5ns. The sample/hold
front-end of a 12-bit 50MSample/s ADC was implemented
with this OPAMP. It achieves an SNR of 78dB for an 8.1MHz
input signal.

semico_ljj

by
Jie Yuan, Nabil Farhat

Electrical and System Engineering Department
University of Pennsylvania

semico_ljj

5. CONCLUSION
A design methodology for a gain-boosted OPAMP is presented.
The settling performance of the gain-boostedOPAMP
will be subject to two potential problems: the presence of
the doublet and instability, which involves the pole-zero evolution
shown in Fig. 7. The methodology enables designers
to strike a balance between the two problems so as to
achieve optimal OPAMP design in terms of settling performance.
A sample telescopic gain-boosted OPAMP is designed
using this methodology. The exact characteristics are shown
in Table 1. The sample/hold front-end in Fig. 3 using OPAMP1
can achieve an SNR of 78dB with an input signal of 8.1MHz
in frequency and 2Vp−p in amplitude.

semico_ljj

6. REFERENCES
[1] D. Johns and K. Martin, Analog Integrated Circuit Design,
John Wiley & Sons, New York, 1997
[2] K. Bult and G. Geelen, “A Fast-Settling CMOS Op Amp for
SC Circuits with 90-dB DC Gain”, IEEE J. Solid-State Circuit,
vol. 25, pp.1379-1384, Dec., 1990
[3] B.J. Hosticka, “Improvement of the Gain MOS Amplifiers”,
IEEE J. Solid-State Circuits, vol. 14, pp. 1111-1114, Dec, 1979
[4] B.Y.Kamath and R.G.Meyer and P.R.Gray, “Relationship Between
Frequency Response and Settling Time of Operational Ampli
fiers”, IEEE J. Solid-State Circuits, vol. SC-9, pp.347-352, Dec.
1974
[5] D. Fandre and A. Viviani, “Improved Synthesis of Gain-Boosted
Regulated Cascode CMOS Stages Using SymbolicAnalysis and
gm/ID Methodology”, IEEE J. Solid-State Circuits, vol. 32, pp.
1006-1012, Jul. 1997

litaeng

very nice

CDS

谢谢楼主分享！

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