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《Application_Manual_for_Power_Supply_Noise_Suppression_and_Decoupling for Digital ICs》
关于片内供电网络设计的书
Contents
1. Introduction 1
2. Generation of power supply noise from digital ICs and configuration of decoupling circuits 4
2.1 Mechanism of power source noise generation 4
2.2 Various ways to view the noise and evaluation criteria 5
2.3 Measurement method for insertion loss 7
2.4 Bypass (decoupling) capacitor 8
2.5 Inductors, ferrite beads 9
2.6 Capacitance necessary for a capacitor 11
3. Noise suppression with a capacitor 12
3.1 Frequency characteristics of the capacitor 12
3.2 Influence of the capacitor mounting pattern 13
3.3 Noise path and capacitor mounting position 14
3.4 Influence of peripheral circuit impedance 17
3.5 Parallel connection of capacitors and antiresonance 18
.......
7. Location of a capacitor for suppressing power supply impedance 56
7.1 Power supply impedance relative to an IC 56
7.2 Simple estimation of power supply impedance relative to an IC 57
7.3 Possible range for placing the closest capacitor of an IC 58
7.4 Guideline for the maximum allowable wiring length, lmax 60
8. Configuration of PDN combined with capacitors 64
8.1 Hierarchical positioning of decoupling capacitors 64
8.2 Impedance of PDN 65
8.3 Hierarchical positioning of capacitors 66
8.4 Target impedance on PCB 69
8.5 Bulk capacitor 69
8.6 Board capacitor 70
8.7 Capacitance design of a capacitor 72
8.8 Making a PDN with ultra-low impedance 76
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发表于 2011-7-21 16:37:34
