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芯片精品文章合集(500篇!)    创芯人才网--重磅上线啦!
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[招聘] 联发科招聘IC相关职位(北京/成都)

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发表于 2011-7-12 18:26:01 | 显示全部楼层 |阅读模式

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Job Title: Senior design verification methodology engineer
Location: Beijing/Chengdu
Job description:
1. Setup advanced asic design verification methodology/working flow.
2. Apply advanced verification methodology to complex module/sub-system verification.
3. Keep in touch with  EDA vendors to keep the leading position of design verification methodology.        
4. Central complex design IP verification.

Requirement:
1. Ms Degree in Microelectronics/Electrical Engineering/Computer Science.
2. Minimum 1 years of ASIC design/verification experience.   
3. Familiar with one of Contraint Random Verification(CRV) methodologies - VMM/OVM/UVM.
4. Familiar with SOC architecture and AMBA specification is a plus.
5. Experience of developing complex VIP is a plus.
6. Experience of applying CRV on complex module/subsystem verifications is a plus.   
7. Experience of hardware acceleration technique is a plus.(Beijing)
8. Familiar with Tcl/Perl is a plus.
9. Knowledge of SD/Ethernet/USB protocol is a big plus.(Chengdu)

職缺名稱(中文): SOC周邊數位高級IC設計工程師 (急招)
職缺名稱(英文): SOC Peripherals Digital IC Designer
職缺類別: 研發工程
工作地点:成都
需求人數: 3人
學歷要求: 碩士以上
工作年資: 1年以上
工作內容(中文):
1.SoC整體系統架構設計及RTL實現
2.SOC周邊區塊之架構設計及RTL實現
3.熟悉IC設計流程, FPGA驗證流程, 和SoC系統整合
4.具以下任一專長者尤佳
    -> USB, SDIO or Memory Card controller
    -> WiFi MAC, Ethernet MAC, Security Engine, DRAM or Flash controller
    -> 具Embedded processor MCU/dsp相關經驗
    -> 具system performance analyze with ESL相關經驗

Job Title:Digital front-end EDA Methodology Engineer
Location: Beijing
Education:Master’s Degree
Job contents:
1.Keep in touch with EDA vendors to keep the leading position of design methodology
2.Work with design methodology team to setup and develop advanced design methodology/flow/tools.
3.Co-work with design team to deploy the advance methodologies.
4.Support design teams’ daily implementation process and solve design teams’ tough questions.

Requirement:
1.Familiar with usage of EDA tools, experience of chip integration, familiar with IC design flow.
2.Experience in writing script with Makefile/Tcl/Perl/etc, experience in C/C++.
3.Good verbal and written communication and presentation skills in English.
4.Can focus on details and solve problem carefully, willing to take responsibility to help other engineers.
5.2+ year EDA software development experience is a plus. Have knowledge of EDA algorithm is a plus.
6.Experience in IC design is a plus.
 楼主| 发表于 2011-7-13 12:27:27 | 显示全部楼层
忘写了,如有兴趣,请将简历发至 tao.liu@mediatek.com
发表于 2011-7-14 09:53:11 | 显示全部楼层
北京和成都两地的待遇如何
发表于 2011-7-14 20:20:23 | 显示全部楼层
关键是待遇,好多钱的问题都没说
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