sram接口设计：pipeline和flow-through 区别

wave654321

小弟最近在写通用存储器接口，想问一下有关SRAM的问题：SRAM构建中，PIPELINE和FLOW-THROUGH有什么区别？

Lawee

PIPELINE： 在w_n有效两个周期后才能写数据、或者 获得读数据了
FLOW-THROUGH：则是在w_n有效后一个周期后

yuwangbj

Flow-through dual-ports allow data access without latency. In other words, data from a read is returned on the same clock cycle the read instruction is issued. This is advantageous in applications where access time to a single piece of data is critical. Unfortunately, reading the memory array and returning a value in the same cycle results in a slower operating frequency, and therefore lower device bandwidth. Pipelined dual-ports increase device bandwidth by breaking the read operation into 2 steps. The memory array is accessed during the first clock cycle. The read data is registered and driven to output in the second cycle. As a result, pipelined devices have 1 cycle of latency to read data. However, by breaking the access into 2 steps the clock cycle can be shorted and device bandwidth increased. There is usually no difference in write operations between flow-through and pipelined devices. In future devices, additional pipeline stages may be added. In this case, the read latency will increase to three, four, or more cycles, but this allows continued improvement in device bandwidth.

yuwangbj

Pipelined SRAMs: Pipelined 和flow-through SRAM的区别是，pipelined器件在输入和输出端都有一个寄存器。在读操作时，数据可以流入pipeline器件输出寄存器。在下一个时钟周期，数据锁存在器件输出端。这和flow-through器件有所区别，这是因为从pipelinedSRAM 出来的数据会比flow-through的晚一个周期。然而，pipeline器件可以工作在比flow-through器件更高的频率，因为访问会有几个周期的中断。pipeline器件的写操作和flow-through器件相同。

ttxxmm

学习了

cdsmakc

前者比后者在输出级上多了一组寄存器。可以把块RAM理解成一个组合逻辑，当你地址给到RAM的地址端口时，地址立刻选中了存储单元，存储单元将数据放置在了RAM的输出数据端口上。如果插入一级寄存器，这些数据显然要经过一个时钟周期，即地址准备好后的下一个周期可以看到数据。这个寄存器不管是altera还是xilinx，都是封装 在块RAM的内部的，是否使用由用户确定。分析寄存器到寄存器的时序路径：准备地址的寄存器到块RAM的布线延时、块RAM的响应延时、块RAM到LAB或者CLB内寄存器的布线延时。这个时间是比较长的。我们假设Xilinx使用前者模式 或者 ALTERA使用ACK模式，在这路径中插入了一级寄存器，分割了原本较长的时序路径，我认为这是Pipelined和非ACK模式能运行在一个高频率的 原因 。

Smile_HP

学习了，谢谢！

zrseu

学习了学习了