求助一下这个程序是怎么错的？

libra811

module cvbs(clkin,clkout);
input clkin;
output clkout;
reg clkout;
//***********************************//
integer i;
always @(*)
for(i=0;i<5;i=i+1)
begin
v_pluse(clkin,clkout);
  end
//**********实现场同步脉冲(M=512)**********//
task v_pluse;
input  clkin;
output clkout;
reg [9:0] M=512;
reg [15:0] count=0;
always @(posedge clkin)
  begin
      if (count==(M-1))
         count=0;
       else
          count=count + 1;
  end
always
begin
  if (count==437)
      clkout=count[8];
  else if (count==0)
   clkout=count[8];
end
endtask
endmodule
下面是报的错：
Error (10170): Verilog HDL syntax error at cvbs.v(21) near text "always";  expecting ";", or "@", or an identifier ("always" is a reserved keyword ), or a system task, or "{", or a sequential statement,
Error (10170): Verilog HDL syntax error at cvbs.v(28) near text "always";  expecting ";", or "@", or an identifier ("always" is a reserved keyword ), or a system task, or "{", or a sequential statement,

[ 本帖最后由 libra811 于 2006-10-30 22:43 编辑 ]

libra811

自己顶一下
主要是事件控制的问题
不是很明白