想学SystemVerilog的就下吧！

sinva · 发表于 2011-5-28 17:19:42

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想学习SystemVerilog 的就down下了看看吧，这是一个同步FIFO的SystemVerilog 设计，包括RTL 、testbench、assertion，一定会对你有帮助的！Enjoy!

sdustyj · 发表于 2011-5-28 19:06:15

希望能起到启蒙作用

ジ爱の约定 · 发表于 2011-5-29 09:15:23

感谢楼主的贡献，希望对自己有帮助！

sinva · 发表于 2011-5-30 19:25:49

回复 1# sinva

When someone gets involved with SystemVerilog at firt time, they may be confused and curious of how to use SystemVerilog to write RTL, testbench, coverage, assertion etc. In the example I offered, I showed you the elegent coding style to model with SystemVerilog, you may learn how to use and think in object-oriented way to write your testbench, and how to bind assertions to the DUT. I'll offer you some other examples later.
At last, I'm glad to interact with every enthusiast!!!