The Challenge of Signal Integrity in Deep-Submicrometer CMOS Technology

drjiachen

Invited Paper

Advances in interconnect technologies, such as the increase
in the number of metal layers, stacked vias, and the reduced
routing pitch, have played a key role to continuously improve
integrated circuit density and operating speed. However, several
parasitic effects jeopardize the benefits of scale-down.
Understanding and predicting interconnect behavior is vital for
designing high-performance integrated circuit design. Our paper
first reviews the interconnect parasitic effects and examines their
impact on circuit behavior and their increase due to lithography
reduction, with special emphasis on propagation delay, lateral
coupling, and crosstalk-induced delay. The problem of signal
integrity characterization is then discussed. In our review of the
different well-established measurement methodologies such as
direct probing, S-parameters, e-beam sampling, and on-chip
sampling, we point out weaknesses, frequency ranges, drawbacks,
and overall performances of these techniques. Subsequently, the
on-chip sampling system is described. This features a precise
time-domain characterization of the voltage waveform directly
within the interconnect and shows its application in the accurate
evaluation of propagation delay, crosstalk, and crosstalk-induced
delay along interconnects in deep-submicrometer technology. The
sensor parts are described in detail, together with signal integrity
patterns and their implementation in 0.18-m CMOS technology.
Measurements obtained with this technique are presented. In
the third part, we discuss the simulation issues, describe the
two- and three-dimensional interconnect modeling problems, and
review the active device models applicable to deep-submicrometer
technologies in order to agree on measurements and simulations.
These studies result in a set of guidelines concerning the choice of
interconnect models. The last part outlines the design rules to be
used by designers and their implementation within computer-aided
design (CAD) tools to achieve signal integrity compliance. From a
0.18-m technology are derived critical variables such as crosstalk
tolerance margin, maximum coupling length, and the criteria for
adding a signal repeater. From these, values for low-dielectric and
copper interconnects have been selected.

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demi81

回复 1# drjiachen

julien3184

谢谢了啊， 最近在关心这方面的东西，感觉好深奥啊

Evgen

smaa

thanls