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部门即将开展一个新的项目,机会很好,想跳槽的朋友可以把简历传给我,合适的话我会直接把你简历传给我们部门老大的。招聘的职位从初级到高级都有,主要是digital design, verification  and enumlation. 硕士两年以上工作经验就OK了。
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 The successful candidate will have a MSEE, BSEE or equivalent degree, should have good understanding on ASIC/SOC design flow and has got design experience with two or more of the following skill sets:
 RTL(verilog) coding and style checking
 makefile, perl, TCL or csh/tcsh scripts
 clock-domain-cross checking
 dynamic logic simulation or post-layout simulation
 logic synthesis or physical Synthesis
 static timing analysis
 logic equivalency checking
 ECO(engineering change order)
 top level integration
 floor planning
 pad-ring design
 clock distribution
 design for test/debug/trace
 It is a plus if the candidate has one or more of the following experience/knowledge:
 X86/ARM/8051 architecture
 PCI-E/PCI bus
 AMBA bus(AXI/AHB/APB)
 USB (3.0/2.0/1.1; HSIC; host/device/OTG)
 NAND/NOR Flash host controller, BCH, or DDR controller
 Audio System
 Clock generation and control
 Low power design
 SD/eMMC host controller
 SATA/SAS
 Legacy (SPI/SMBUS/ACPI/LPC/GPIO)
 General connectivity (I2S/I2C/UART)
 Ethernet
 JTAG
 The candidate must exhibit good verbal and written communication skills in both Chinese and English. Hands-on lab experience is another plus, able to understand and/or use the use scopes, logic analyzers, has knowledge or skill of board-level lab debugging.
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