DFT最后一本经典书Advanced System-on-Chip Test Design and Optimization

mapledove2007

Springer - Introduction to Advanced System-on-Chip Test Design and Optimization.pdf (5.59 MB, 下载次数: 4044 )

2011-4-16 01:06 上传

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这是到目前为止，我手里的最后一本关于DFT设计的书籍。里面的主要内容可能和之前发布的书里的内容有重叠，但是更有利于我们对相关问题的理解。

Preface xiii

Acknowledgements xvii

Part 1 Testing concepts

1. INTRODUCTION 1

2. DESIGN FLOW 5

1 Introduction 5

2 High-level design 6

3 Core-Based Design 7

3.1 Network-on-Chip 9

3.2 Platform-Based Design 9

4 Clocking 10

4.1 System Timing 11

4.2 Clock Distribution 11

4.3 Multiple Clock Domains 12

4.3.1 Phase Locked Loop (PLL) 12

4.3.2 Globally-Asynchronous Locally-Synchronous 13

5 Optimization 14

5.1 Optimization Techniques 16

5.1.1 Backtracking and Branch-and-bound 16

5.1.2 Integer Linear Programming 17

5.1.3 Local Search 17

5.1.4 Simulated Annealing 18

5.1.5 Genetic Algorithms 18

5.1.6 Tabu Search 19

vi SOC Test Design

3. DESIGN FOR TEST 21

1 Introduction 21

1.1 Fault models 21

1.1.1 Stuck-at Fault Model 22

1.1.2 Bridging Fault Model 22

1.1.3 Stuck-Open Fault Model 23

1.1.4 Delay Fault Model 23

1.2 Test Generation for Combinational Circuits 24

1.2.1 Path Sensitization 25

1.2.2 Boolean Difference 25

1.2.3 D-algorithm 26

1.2.4 PODEM (Path-Oriented Decision-Making) 27

1.2.5 FAN (Fanout-Oriented Test Generation) 28

1.2.6 Subscripted D-Algorithm 28

1.2.7 CONcurrent Test Generation 28

1.2.8 Fault Simulation 28

1.2.9 Optimization 28

1.2.10 Delay Fault Detection 30

1.3 Testing Sequential Circuits 30

2 Design-for-Test Methods 31

2.1 Test Point Insertion 32

2.2 The Scan Technique 32

2.2.1 Scan Testing for Delay Faults 36

2.3 Test Pattern Generation for BIST 39

2.3.1 Exhaustive Pattern Generation 40

2.3.2 Pseudo-Random Pattern Generation 40

2.3.3 Pseudo-random-based test generation 40

2.3.4 Deterministic Testing 41

2.4 Test Response Analysis for BIST 41

2.5 Circular-BIST 43

2.6 BIST-Architectures 43

2.6.1 BILBO (Built-In Logic Block Observer), 43

2.6.2 STUMPS Architecture 44

2.6.3 LOCST (LSSD On-Chip Self-Test) 44

2.7 Memory Testing 45

2.7.1 Algorithmic Test Sequence (ATS) 48

2.7.2 Marching Pattern Sequences (MARCH) 48

2.7.3 Checkboard Test 49

2.7.4 Memory BIST 49

2.7.5 Memory Diagnosis and Repair 50

3 Mixed-Signal Testing 51

Contents vii

4. BOUNDARY SCAN 53

1 Introduction 53

2 The Boundary-Scan Standards (IEEE 1149.1) 53

2.1 Registers 56

2.2 TAP Controller 57

2.3 Instructions 57

2.3.1 Example 57

2.3.2 Boundary-Scan Languages 58

2.3.3 Cost of Boundary Scan 58

3 Analog Test Bus (IEEE 1149.4) 61

3.1 Analog Test Access Port (ATAP) 63

3.2 Test Bus Interface Circuit (TBIC) 63

3.3 Analog Boundary Module (ABM) 63

3.4 Instructions 63

3.5 Chaining Example 63

Part 2 SOC Design for Testability

5. SYSTEM MODELING 67

1 Introduction 67

2 Core modeling 68

3 Test Resource modeling 71

4 Core Wrapper 72

5 Test Access Mechanism 74

6. TEST CONFLICTS 77

1 Introduction 77

2 Limitations at the Tester 78

2.1 Bandwidth Limitations 79

2.2 Tester Memory Limitations 79

2.3 Test Channel Clocking 80

3 Test Conflicts 81

3.1 General Test Conflicts 81

3.2 Multiple Test Set 82

3.3 Multiple Sets of Test Sets 82

3.4 Interconnection Testing - Cross-Core Testing 84

3.5 Hierarchy - Cores Embedded in Cores 85

4 Discussion 86

viii SOC Test Design

7. TEST POWER DISSIPATION 89

1 Introduction 89

2 Power consumption 90

3 System-level Power modeling 91

4 Hot-spot modeling with Power Grids 93

5 Core-level Power modeling 95

6 Discussion 98

8. TEST ACCESS MECHANISM 99

1 Introduction 99

1.1 System-on-Chip Test Data Transportation 100

1.1.1 The TestShell and P1500 Approach 100

1.2 Reconfigurable Core Wrappers 106

2 Test Access Mechanism Design 107

2.1 Multiplexing Architecture 108

2.2 Distribution Architecture 109

2.3 Daisychain Architecture 110

2.4 Test Bus Architecture 111

2.5 TestRail Architecture 111

2.6 Flexible-Width Architecture 112

2.7 Core Transparancy 112

3 Test TIME Analysis 113

9. TEST SCHEDULING 115

1 Introduction 115

2 scheduling of Tests with fixed test time under test conflicts 119

2.1 Preemptive test scheduling 128

3 scheduling of tests with non-fixed (variable) testing times 128

3.1 Idle Types 128

3.1.1 Imbalanced TAM Test Completion Times 129

3.1.2 Module Assigned to TAM of Non Pareto Optimal

Width 130

3.1.3 Imbalanced Scan Chains in Module 131

3.1.4 Other Types of Idle Bits 131

3.2 SOC Test Scheduling with Fixed-Width TAM 132

3.3 SOC Test Scheduling with Flexible-Width TAM 134

3.3.1 Test Power 137

3.3.2 Multiple Test Sets 138

Contents ix

3.4 Other Test Scheduling Techniques 138

3.4.1 Problem: Control lines and Layout. 138

3.4.2 Problem: Power Modeling 138

3.4.3 Problem: Fixed Test Resources 139

3.4.4 Problem: Multiple Clock Domains 140

3.4.5 Problem: Delay Fault Testing 140

3.4.6 Defect-Oriented Scheduling 140

4 Optimal Test time? 143

4.1 Soft Cores - No Fixed Scan-chains 146

4.2 Hard Cores - Fixed Number of Scan-chains 150

5 Integrated Test Scheduling and TAM Design 151

5.1 Test Time and Test Power Consumption 152

5.2 Bandwidth Assignment 152

5.3 Test Scheduling 153

5.4 TAM Planning 154

5.5 TAM Optimization 156

6 Integrating Core Selection in the Test Design Flow 157

7 Further Studies 160

7.1 Combined Test Time and TAM Design Minimization 160

7.2 Core Selection in the Test Design Flow 160

7.3 Defect-Oriented Test Scheduling 160

Part 3 SOC Test Applications

10. A RECONFIGURABLE POWER-CONSCIOUS CORE WRAPPER

AND ITS APPLICATION TO SYSTEM-ON-CHIP TEST

SCHEDULING 163

1 Introduction 163

2 Background and Related Work 165

3 A Reconfigurable Power-Conscious Core Wrapper 167

4 Optimal Test Scheduling 170

4.1 Optimal Scheduling of Core Tests 171

4.2 Transformations for Optimal TAM Utilization 173

4.3 Cross-Core Test Scheduling 175

4.4 Optimal Power-Constrained Scheduling 177

4.5 Minimization of TAM Wiring 179

5 Experimental Results 180

6 Conclusions 182

x SOC Test Design

11. AN INTEGRATED FRAMEWORK FOR THE DESIGN AND OPTIMIZATION

OF SOC TEST SOLUTIONS 187

1 Introduction 187

2 Related Work 188

3 System modeling 192

4 The SOC Test Issues 194

4.1 Test Scheduling 194

4.2 Power Consumption 195

4.3 Test Source Limitations 197

4.4 Test Set Selection 197

4.5 Test Access Mechanism 198

4.6 Test Floor-planning 200

5 The Heuristic Algorithm 201

6 Simulated Annealing 205

6.1 The Simulated Annealing Algorithm 205

6.2 Initial Solution and Parameter Selection 206

6.3 Neighbouring Solution in Test Scheduling 206

6.4 Neighbouring Solution in Scheduling and TAM Design 206

6.5 Cost function 207

7 Experimental Results 208

7.1 Benchmarks 208

7.2 Test Scheduling 208

7.3 Test Resource Placement 209

7.4 Test Access Mechanism Design 209

7.5 Test Scheduling and TAM Design 211

8 Conclusions 214

12. EFFICIENT TEST SOLUTIONS FOR CORE-BASED DESIGNS 215

1 Introduction 215

1.1 Introduction 215

2 Background and Related Work 217

3 Test Problems 221

3.1 Test Time 221

3.2 Test Power Consumption 226

3.3 Test Power Consumption at Test Parallelization 229

3.4 Test Resource Limitations 230

3.5 Test Conflicts 231

3.6 Test Access Mechanism Design 232

3.7 System Modeling 233

Contents xi

4 Our Approach 237

4.1 Bandwidth Assignment 238

4.2 Test Scheduling 239

4.3 TAM Planning 240

4.4 An Example 242

4.5 TAM Optimization 244

4.6 Complexity 246

5 Experimental Results 246

5.1 Test Scheduling 246

5.2 Integrated Test Scheduling and TAM Design 247

5.3 Test Scheduling, Test Parallelization and TAM Design 249

6 Conclusions 250

13. CORE SELECTION IN THE SOC TEST DESIGN-FLOW 253

1 Introduction 253

2 BACKGROUND 254

3 Related Work 257

4 Problem Formulation 260

4.1 Problem Complexity 263

5 Test Problems and Their Modeling 263

5.1 Test Time 263

5.2 Test Power Consumption 264

5.3 Test Conflicts 267

6 Test Design Algorithm 268

6.1 Resource Utilization 271

6.2 Example 271

7 Experimental Results 273

8 Conclusions 275

14. DEFECT-AWARE TEST SCHEDULING 277

1 Introduction 277

2 Related Work 278

3 Sequential Test Scheduling 279

4 Concurrent Test Scheduling 280

4.1 Test Sets with Fixed Test Times 281

4.2 Test Sets with Flexible Test Times 282

4.3 Test Scheduling Algorithms 283

5 Experimental Results 286

xii SOC Test Design

6 Conclusions 286

15. AN INTEGRATED TECHNIQUE FOR TESTVECTOR SELECTION

AND TEST SCHEDULING UNDER ATE MEMORY DEPTH

CONSTRAINT 291

1 Introduction 291

2 Related Work 293

3 Problem Formulation 295

4 Test Quality Metric 296

5 Test Scheduling and Test Vector Selection 299

5.1 Illustrative Example 301

5.2 Optimal Solution For Single TAM 305

6 Experimental Results 305

7 Conclusions 307

Appendix 1. Benchmarks 321

1 Introduction 321

2 Format of the inputfile 321

3 Design Kime 324

4 Design Muresan 10 326

5 Design Muresan 20 327

6 ASIC Z 329

7 Extended ASIC Z 331

8 System L 333

9 Ericsson design 335

10 System S 349

References 353

Index 383

mapledove2007

版主，我好像发错区啦，如果有违反规定请删除，我在到IC test and verification区发布。

xlteam2

thanks for sharing

mtwumtwu

good reference

过路心客

Thanks for sharing

lujunfeng111

这本书是哪一年出版的？

scorpion

thanks a lot

ysliu168

Thanks!

mapledove2007

回复 7# lujunfeng111


    具体年限，书上都有，我是从boss那儿要来的。谢谢！

何世青

thanks