美资跨国芯片公司急招Sr. ASIC Design Engineer（上海）

KT咨询-IC电子

联系顾问：Email&MSN:   Digital1@kthr.com，本职位系统编号：121135922156  
招聘岗位：Sr. ASIC Design Engineer
工作地点：上海

岗位描述：
Job Duties:
Responsible for DTV/STB multi-format video codec hardware module development and support. This video codec hardware core will worked together with embeded MIPS/ARM CPU to implement real-time high-definition encoding, decoding and transcoding functions of input bitstreams or video sequence.

职位要求：
Qualifications:
B.S/M.S degree in Computer Science or Micro-electronics or equivalents
Be familiar with design flow for ASIC chip design, skillful in RTL coding, synthesis and timing analysis
Be Familiar with video compression/decompression algorithms and multimedia applications.
Good knowledge in embedded system design.
Team player and self-driven.
Fluent in written and spoken English.
Any of the followings will be a good plus and preferred:
Have 2+ years experience in hardware development for video decode/encode or related projects.
Have skills in FPGA development
Skillful in C/C++ programming language.
Have certain knowledge on SoC HW and DSP.  

本文来源于“胡说IC”论坛，欢迎访问去了解更多IC电子通信工程师职业咨询问题和高薪热招职位！

wangjunweiair

Dark-Killer

a 好行业，，，要求经验呢

#1bookworm

ding~~~~

xuguanjian

ding~~~~

KT咨询-IC电子

美资老牌IC公司急聘digital design engineer
联系顾问E-mail&MSN：digital1@kthr.com
本职位系统编号：121174729375
工作地点：北京

岗位描述：
Responsibility:
Participate in mix-signal IC development high speed mix signal products, working with multi-site engineers on different functions such as analog design, application, product evaluation and layout. The incumbent is expected to contribute to signal chain understanding/partition, algorithm development, design, verification, synthesis, timing and power analysis. And he/she is also required be able to understand the inputs from application engineers to translate real world issues to design requirements. Some basic lab skill to work with product evaluation engineers and understanding real silicon issue is also needed.

职位要求：
Requirement:
MSEE or above in EE related majors
At least 2-3 years working experience on RTL related design, verification and implementation for FPGA or ASIC. Real mixed signal ASIC experience is preferred. High speed design experience is a strong plus but not necessary required.
Knowledge on signal processing is a strong plus. The candidate should know well on sampling theory, filter design, and some of algorithm development skills.
Have FPGA or real silicon experience and have chance to look at silicon functions and performance with good silicon debugging skills.
Have basic system understanding of converters/PLL or at signal chain level.
Self motivated, result oriented, team player and good communication skills.
Solid problem solving skills and leadership experience are appreciated.
Good spoken and written English
  
本文来源于“胡说IC”