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Staff Physical Verification Engineer Responsibilities: Assist multiple Zoran design groups in physical verification (DRC/LVS/ERC/Antenna), chip-level layout and tapeout reviews, as well as maintaining physical verification flow, layout and add-on tools. You also will take physical design (P&R) projects from time to time. Qualifications: Expert user of Cadence Virtusso, Laker or Mentor IC-Station. Expert user of Mentor*s Calibre or Synopsys* Hercules runsets or ruledecks creation and debugging. Must be programming-minded capable of writing Tcl or Perl. In-depth understanding of fabrication processing steps used in major foundries.
Proven track records of working independently on running and debugging chip-level DRC/LVS/ERC/Antenna results. Self-motivated team worker, good verbal and written communication skills. Knowledge of Synopsys Place-and-Route tools Must able to work under tapeout pressure and tight schedule 8+ years of direct experience on IC layout, physical verification and tapeout (MS 6+years) 工作地点:上海 公司性质:美资原厂 MSN:cavell2010@hotmail.com |