Positionhysical Design Engineer(VLSI)
工作地点： 上海
语言要求： 英语
学 历： 本科
职位描述
1~3years VLSI experience
Experience with one of the major P&R (Place & Route) tool suites (Cadence, Synopsys, Mentor, or Magma).
Good understanding of timing closure and signoff (PrimeTime experience preferred).
Scripting expertise (Perl, Tcl, or Python) a plus
Understanding of toplevel (SoC) hierarchical design issues.
Skills:
-Experienced with tape out
- Experienced with common EDA Tools flow, preferable Synopsys
- Skills in Linux, tcl and/or perl
- Basic understanding of CMOS VLSI IC design and timing
- Minimum 5 years of tape out related working experience
- Education: MS/BS in EE or CS or Physics
Job Description:
Improve APR flow
- Participate APR work from netlist to GDSII
- Generate timing/power related reports and achieve timing/power closure.
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发表于 2011-3-9 15:13:32
hysical Design Engineer(VLSI) 
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