FPGA IO问题

cuichenhust

我想把寄存器放入IOE里边以保证FPGA与其他器件的时序。要实现此功能需要使用assignment editor将相应的pin设置成fast IO。
以下为设置成fast IO的要求：
1.Fast Input Register option
A logic option that implements an input register in an I/O cell that has a fast, direct connection from an I/O pin. Turning on the Fast Input Register option can help maximize I/O timing performance, for example, by permitting fast setup times. Turning off this option for a particular signal prevents the Fitter from implementing the signal automatically in an I/O cell.
This option must be assigned to either a register or an input or bidirectional pin that feeds a register or it is ignored. This option is available for all Altera devices except FLEX 6000, HardCopy, and MAX 3000 devices.

2.Fast Output Enable Register
A logic option that implements an output enable register in an I/O cell with a fast, direct connection to an I/O pin. Turning on the Fast Output Enable Register option can help maximize I/O timing performance, for example, by permitting fast clock-to-output enable times. Turning this option off for a particular signal prevents the Fitter from implementing the signal automatically in an I/O cell.
This option must be assigned to either a register or an output or bidirectional pin that has a tri- state buffer controlled by a register or it is ignored. This option is available for all Altera devices supported by the Quartus II software expect MAX 3000 and MAX 7000 devices.


我的设置1：
先通过assignment editor的node finder(pins:input)设置了输入，然后(pinsutput)设置了输出（顶层的input/output pins都是wire型的，但都直接与寄存器连接着），查看fitter的messages，发现input和output都没有将寄存器打包到IOE里。
我的设置2：
通过assignment editor的node finder(register:post-fit)设置了与输入连接的寄存器，然后(register:post-fit)设置了与输出连接的寄存器，查看fitter的messages，发现output打包到IOE里，input没有。

研究了很长时间毫无进展，请高手们指点如何将input register打包进IOE中！！！！！！！！！

PS：我使用quartusII10.1，如果采用“我的设置1”，将会产生一个warning，报告说fast IO的约束被忽略，而使用quartusII9.0这个信息将出现在info中，不容易察觉。

zsan566

帮你顶一下！

dandan8668

是Xilinx的板子吗？？？