分享一个好东西：verilog代码美化工具

idbi · 发表于 2011-1-16 16:19:44

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试用过了，不错！

How to use : perl ind_verilog.pl my_code.v

==== Author: Pinhas Krengel
==== This source file may be used and distributed without ====
==== restriction provided that this copyright statement is not ====
==== removed from the file and that any derivative work contains ====
==== the original copyright notice and the associated disclaimer.====

Daniel10003 · 发表于 2011-1-16 18:24:06

呵呵，谢谢楼主

Daniel10003 · 发表于 2011-1-16 18:26:47

呵呵，谢谢楼主

gdarboux · 发表于 2011-1-16 21:01:44

什么情况？貌似什么都没有啊

fly123456 · 发表于 2011-1-16 23:19:28

怎么下？奇怪

pipida · 发表于 2011-1-17 05:53:09

我来帮帮楼主

ASIC/FPGA Design and Verification Out Source Services

Code Indentation

The following set of scripts indent a code, which is written in e (specman) or verilog or vhdl. The motivation for indentation is to have all code with the same indentation using spaces only (no TABs). Using spaces for indentation makes the indentation independent of the editor and its configuration, which is used.
Sometimes a block of code is not complete, be it VHDL, verilog or specman, and it is difficult to find where a {} (e) is missing. When running the script, it would try to find the number of first mis-match. The default indentation size is two spaces.
The script modified output file is written always to a file named 2.e. The user than should use diff -w and confirm the changes.

How to use : perl ind.pl my_code.e
How to use : perl ind_verilog.pl my_code.v
How to use : perl ind_vhdl.pl my_code.vhd

Note: if the file is in DOS format, you may want to first run dos2unix on the file.

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