ieee paper

shaweikang1984

Improving Multi-Level NAND Flash Memory
Storage Reliability Using Concatenated
BCH-TCM Coding


Abstract—By storing more than one bit in each memory cell,
multi-level per cell (MLC) NAND flash memories are dominating
global flash memory market due to their appealing storage density
advantage. However, continuous technology scaling makes
MLC NAND flash memories increasingly subject to worse raw
storage reliability. This paper presents a memory fault tolerance
design solution geared to MLC NAND flash memories. The basic
idea is to concatenate trellis coded modulation (TCM) with an
outer BCH code, which can greatly improve the error correction
performance compared with the current design practice that
uses BCH codes only. The key is that TCM can well leverage the
multi-level storage characteristic to reduce the memory bit error
rate and hence relieve the burden of outer BCH code, at no cost
of extra redundant memory cells. The superior performance of
such concatenated BCH-TCM coding systems for MLC NAND
flash memories has been well demonstrated through computer
simulations. A modified TCM demodulation approach is further
proposed to improve the tolerance to static memory cell defects.
We also address the associated practical implementation issues
in case of using either single-page or multi-page programming
strategy, and demonstrate the silicon implementation efficiency
through application-specific integrated circuit design at 65 nm
node.

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zh123456789

谢谢啊

shaweikang1984

jimmycmwu0

Thanks! Thanks!  Thanks!