PLL与DLL设计教程

chipdesign

TI信号链专区正式上线，欢迎访问！

luckybreeze123

不知道如何，下来看看吧！

mczhangheng

thx a lot

chipdesign

[Examination flow]

1) Voltage fluctuation resulting from a mismatch between the M1 and

M2 elements (See the theoretical equation (3))

2) Current fluctuation resulting from a mismatch between the M3 and

M4 elements (See the theoretical equation (4))

3) Systematic offset addition resulting from fluctuations in constant

current of M3 and M4

For many circuits, the relationship between Vg and Id can be defined by considering it in a combined way according

to the fluctuations set forth in (1) to (4) above.

chipdesign

1) Voltage fluctuation resulting from a mismatch between the M1 and

M2 elements (See the theoretical equation (3))

2) Current fluctuation resulting from a mismatch between the M3 and

M4 elements (See the theoretical equation (4))

3) Systematic offset addition resulting from fluctuations in constant

chipdesign

1) Voltage fluctuation resulting from a mismatch between the M1 and

M2 elements (See the theoretical equation (3))

2) Current fluctuation resulting from a mismatch between the M3 and

M4 elements (See the theoretical equation (4))

3) Systematic offset addition resulting from fluctuations in constant

chipdesign

1) Voltage fluctuation resulting from a mismatch between the M1 and

M2 elements (See the theoretical equation (3))

2) Current fluctuation resulting from a mismatch between the M3 and

M4 elements (See the theoretical equation (4))

3) Systematic offset addition resulting from fluctuations in constant

chipdesign

1) Voltage fluctuation resulting from a mismatch between the M1 and

M2 elements (See the theoretical equation (3))

2) Current fluctuation resulting from a mismatch between the M3 and

M4 elements (See the theoretical equation (4))

3) Systematic offset addition resulting from fluctuations in constant

子学

感谢楼主！！

子学

谢楼主分享！！