SUBMICRON CMOS COMPONENTS FOR PLL BASED FREQUENCY SYNTHESIS

x1346

Table of Contents
Chapter 1: Introduction ...................................................................................................1
1.1 Chapter overview.....................................................................................................1
1.2 Introduction..............................................................................................................1
1.3 Focus of the thesis....................................................................................................2
1.4 Thesis motivation .....................................................................................................2
1.5 List of contributions .................................................................................................3
1.6 Organization of the thesis ........................................................................................4
Chapter 2: Frequency Synthesis and Phase-Locked Loops ..........................................6
2.1 Chapter overview.....................................................................................................6
2.2 Definition of an ideal frequency synthesizer ...........................................................6
2.3 Brief history .............................................................................................................6
2.4 Frequency synthesis: Needs and challenges ............................................................7
2.5 Basic operations in frequency synthesis ..................................................................8
2.5.1 Frequency multiplication .............................................................................8
2.5.2 Frequency division.......................................................................................8
2.5.3 Frequency addition and subtraction: mixing................................................9
2.5.4 Frequency filtering .......................................................................................9
2.6 Frequency synthesizer performance criteria ..........................................................10
2.6.1 Phase noise.................................................................................................11
2.7 Frequency synthesis classification .........................................................................15
2.8 Linearized transfer functions for the integer-N PLL-FS........................................16
2.8.1 Order/type of phase-locked loops ..............................................................19
2.8.2 Choices available for a loop-filter ..............................................................19
2.8.3 Transfer functions of the 3rd-order, type-II, PLL-FS .................................19
2.8.4 Second-order representation of a third-order system.................................23
2.8.5 System-level and circuit parameters for the 2nd-order loop.......................24
2.8.6 Effect of feedback division ratio on the loop-filter values .........................25
2.8.7 Acceptable range for the damping coefficient ...........................................26
2.8.8 Acceptable range for wn as a fraction of fref..............................................27
2.8.9 Acceptable range for loop-filter resistor, R2 ..............................................28
2.8.10 Noise performance and noise transfer functions........................................29
2.8.11 Dynamic loop-response .............................................................................32
2.9 Publications on CMOS PLL-based synthesizers ...................................................33
2.10 Summary................................................................................................................37
Chapter 3: System Design of the PLL-FS .....................................................................38
3.1 Chapter overview...................................................................................................38
3.2 Fabrication technology and FS architecture ..........................................................38
3.3 Intended applications .............................................................................................39
3.4 Target specifications...............................................................................................39
3.5 System overview of the chosen architecture..........................................................40
3.6 Acquisition of lock.................................................................................................40
3.6.1 Definitions of important terms ...................................................................41
3.6.2 Pull-in range for the CP-based PLL-FS .....................................................41
3.6.3 Hold-in range for the CP-based PLL-FS ...................................................41
3.6.4 Lock-range for the CP-based PLL-FS .......................................................41
3.6.5 Pull-in time ................................................................................................42
3.6.6 Lock-time...................................................................................................42
3.6.7 Total acquisition time.................................................................................42
3.7 Survey of relevant publications on acquisition time ..............................................43
3.8 Proposed new PFD/acquisition-aiding mechanism ...............................................44
3.9 Phase and frequency detectors ...............................................................................45
3.9.1 Duty-cycle limitation for a dual PFD.........................................................48
3.9.2 Solution to the duty-cycle problem............................................................49
3.9.3 Optional reference feedthrough at 2fref ......................................................50
3.10 Design procedure for the APFD ............................................................................50
3.10.1 Arriving at the methodology ......................................................................51
3.10.2 Design methodology for the Agile-PFD (or APFD)..................................53
3.10.3 Reference feedthrough revisited ................................................................55
3.10.4 Power dissipation in the three PFDs ..........................................................56
3.10.5 Maximum operating frequency of a PFD ..................................................56
3.10.6 Output characteristics of the three PFDs ...................................................57
3.10.7 Deadzone simulation..................................................................................58
3.10.8 Functional simulations ...............................................................................58
3.11 Lock detection overview........................................................................................61
3.12 New acquisition-aiding methodology - AgileLock................................................62
3.12.1 The reset pulse ...........................................................................................63
3.12.2 Stability considerations for the AgileLock ................................................64
3.12.3 Advantages of the AgileLock methodology ..............................................65
3.13 PLL-FS system design and practical tips...............................................................65
3.13.1 Frequency planning....................................................................................66
3.13.2 Initial planning and considerations ............................................................67
3.13.3 System design of the PLL-FS ....................................................................68
3.13.4 Simulating loops with monolithic loop-filters ...........................................72
3.13.5 Compensating for loop-parameter variations.............................................72
3.14 Test-set for verifying AgileLock............................................................................73
3.15 Typical second-order step-response equations.......................................................74
3.16 Methodology for the reduction of acquisition time ...............................................74
3.17 Comparison of acquisition techniques ...................................................................78
3.18 Discussion of the PLL-FS acquisition results........................................................81
3.19 Summary................................................................................................................82
Chapter 4: Circuit Design and Simulation Techniques ..............................................83
4.1 Chapter overview...................................................................................................83
4.2 Submicron implementation of the PLL-FS components .......................................83
4.2.1 PFD ............................................................................................................84
4.2.2 Chargepump...............................................................................................84
4.2.3 Suitability of loop-filter integration ...........................................................89
4.2.4 Reference and feedback dividers ...............................................................92
4.2.5 Voltage-controlled oscillator ......................................................................95
4.2.6 Rail-to-rail VCO (VCO5) ........................................................................100
4.2.7 Bandgap reference ...................................................................................103
4.2.8 Lock-detection circuit ..............................................................................104
4.2.9 Acquisition-aiding circuitry .....................................................................106
4.2.10 Interface circuitry.....................................................................................108
4.3 Simulation techniques..........................................................................................109
4.3.1 General simulations .................................................................................109
4.3.2 PFD ..........................................................................................................110
4.3.3 Loop-filter ................................................................................................110
4.3.4 Divider .....................................................................................................110
4.3.5 VCO.........................................................................................................111
4.3.6 Bandgap reference ...................................................................................112
4.3.7 Lock-detection circuit ..............................................................................113
4.3.8 Acquisition-aiding circuitry .....................................................................113
4.3.9 Interface circuitry.....................................................................................113
4.4 Summary..............................................................................................................114
Chapter 5: Test Setups and Performance Evaluation ...............................................115
5.1 Chapter overview.................................................................................................115
5.2 Road-map of the fabricated chips ........................................................................115
5.2.1 ICECUIR0................................................................................................116
5.2.2 ICECUIR1................................................................................................117
5.2.3 ICECUIR2................................................................................................118
5.2.4 ICFCUIR2................................................................................................119
5.3 Test equipment .....................................................................................................120
5.4 Printed circuit boards ...........................................................................................121
5.5 Test setups ............................................................................................................121
5.5.1 Monitoring high-frequency signals off-chip ............................................121
5.5.2 Loop-filter ................................................................................................122
5.5.3 PFD ..........................................................................................................123
5.5.4 Divider .....................................................................................................124
5.5.5 VCO.........................................................................................................125
5.5.6 Bandgap reference ...................................................................................126
5.5.7 Detection of lock and measurement of acquisition time..........................127
5.6 Post-layout simulations and measurement results ...............................................128
5.6.1 PFD ..........................................................................................................128
5.6.2 Loop-filter and fractal capacitors .............................................................130
5.6.3 Divider .....................................................................................................131
5.6.4 Post-scalar ................................................................................................133
5.6.5 VCO1-VCO5 ...........................................................................................133
5.6.6 Bandgap reference ...................................................................................144
5.6.7 Lock-detection circuit ..............................................................................146
5.6.8 Acquisition-aiding circuitry .....................................................................147
5.6.9 Interface circuitry.....................................................................................147
5.6.10 Full PLL-FS post-layout simulations.......................................................147
5.6.11 Power dissipation of the PLL-FS .............................................................148
5.6.12 Full PLL-FS measurements .....................................................................149
5.7 Summary..............................................................................................................150
Chapter 6: Conclusions ................................................................................................151
6.1 Chapter overview.................................................................................................151
6.2 Conclusions..........................................................................................................151
6.3 Problem areas.......................................................................................................152
6.4 Some issues..........................................................................................................152
6.5 Future research.....................................................................................................153
6.6 Summary..............................................................................................................153
Appendix A: Printed Circuit Boards ..........................................................................154
A.1 Modular approach ................................................................................................154
A.2 PCB-ICECUIR0, PCB-ICECUIR1 and PCB-PLLFS .........................................154
A.3 Modular PCBs......................................................................................................156
A.3.1 Power supply filtering ..............................................................................156
A.3.2 Filter PCB ................................................................................................156
A.3.3 RF amplifier PCB.....................................................................................157
A.3.4 Bias PCB..................................................................................................157
A.3.5 Reset PCB ................................................................................................157
A.3.6 Signal PCB...............................................................................................158
A.3.7 (Input-Output) IO-Panel PCB ..................................................................158
A.4 Photographs of the modular PCBs.......................................................................159
Appendix B: Chip Level Schematics, Layouts and Pinouts ......................................160
B.1 ICECUIR0............................................................................................................160
B.2 ICECUIR1............................................................................................................163
B.3 ICECUIR2............................................................................................................166
B.4 Details of probe1/probe2 on ICECUIR2..............................................................167
B.5 Details of probe3 on ICECUIR2..........................................................................168
B.6 Details of probe4 on ICECUIR2..........................................................................169
B.7 Details of probe5 on ICECUIR2..........................................................................170
B.8 Details of probe6 on ICECUIR2..........................................................................171
B.9 Details of probe7 on ICECUIR2..........................................................................172
B.10 Details of probe8 on ICECUIR2..........................................................................173
B.11 Details of probe9 on ICECUIR2..........................................................................174
B.12 Details of probe10 on ICECUIR2........................................................................175
B.13 ICFCUIR2............................................................................................................176
B.14 Floorplan for a typical PLL-FS ...........................................................................177
Appendix C: Component Schematics and Layouts ...................................................178
C.1 Phase-frequency detectors ...................................................................................178
C.2 Chargepump and biasing circuitry .......................................................................181
C.3 VCO1-VCO4 ......................................................................................................186
C.4 VCO5 (rail-to-rail oscillator) ..............................................................................188
C.5 Dividers (Integer-N and fractional-N) ................................................................190
C.6 Lock-detection and acquisition-aiding circuits on ICECUIR1 ...........................195
C.7 Bandgap reference ...............................................................................................197
C.8 Serial-to-parallel converter...................................................................................198
C.9 On-chip buffer......................................................................................................199
C.10 ESD protection module on ICECUIR2................................................................199
C.11 APFD (proposed).................................................................................................200
C.12 Acquisition-aiding circuitry (proposed)...............................................................201
Appendix D: Frequency Synthesizer Types ...............................................................202
D.1 Direct Analog Synthesizers (DAS)......................................................................202
D.2 Direct-Digital Frequency Synthesizers (DDFS) ..................................................205
D.3 Integer-N loops ....................................................................................................209
D.4 Fractional-N loops ...............................................................................................210
D.5 Delay-locked loop frequency synthesizer ............................................................213
D.6 Hybrid loops.........................................................................................................214
References .....................................................................................................................215
SUBMICRON CMOS COMPONENTS FOR PLL BASED FREQUENCY SYNTHESIS.pdf (4.23 MB, 下载次数: 302 )

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CMOS PLL FREQUENCY SYNTHESIS

x1346

不错的论文，虽然是2002年的，但对于学习频综还是挺有价值的。

castrader

下载看看了

gemini06061978

thanks for sharing

jotaro1111

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woyaofengle

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QK168

try run

lujunfeng111

原来是一片论文，内容很丰富啊。

Jason_ke

不错! Thanks