Acknowledgements........................................................................................................................ ii
Table of Contents.......................................................................................................................... iii
Table of Figures ............................................................................................................................ vii
Table of Tables ............................................................................................................................. xii
Chapter 1: Introduction ................................................................................................................... 1
1.1 Motivation............................................................................................................................ 1
1.2 Dissertation Content and Contributions................................................................................ 2
Chapter 2: Characterizing Variability............................................................................................. 4
2.1 Modeling Within-Chip/Across-Chip, Random/Systematic and Dynamic/Static Variability 4
2.2 Sources of Process and Layout-Induced Variation ............................................................... 7
2.2.1 Variations in the Lithography Exposure System ........................................................... 8
2.2.2 Variation in Patterning and Other Manufacturing Steps.............................................. 11
2.3 Process Characterization Methodologies ............................................................................ 12
2.3.1 Frequency..................................................................................................................... 12
2.3.2 Current: I
........................................................................................... 132.4 CAD Tools for Monitor Design Enablement...................................................................... 13
2.4.1 Parametric Yield Simulator (PYS)............................................................................... 14
2.4.2 Pattern Matching Physics............................................................................................. 15
2.5 Design of Gate Lithography Focus Monitors using the Parametric Yield Simulator and
Pattern Matching....................................................................................................................... 18
2.6 Summary ............................................................................................................................. 22
Chapter 3: 45nm Ring Oscillator Monitors Experimental Design................................................ 23
3.1 RO Frequency Sensitivity Analyses for 90nm Test Chip Measurements........................... 23
3.1.1 RO Frequency Sensitivity to Gate Length and Electrical Parasitics............................ 24
3.1.2 RO Frequency Sensitivity to Gate Lithography Dose and Focus ................................ 25
3.1.3 Prediction of RO Sensitivity from PYS Lithography Modeling.................................. 27
3.2 Ring Oscillator Schematics and Floor Plans for 45nm ....................................................... 28
iv
3.3 Summary of the RO Inverter Layouts and the Nomenclature ............................................ 30
3.4 Pattern Matching Guidance for Design of the RO Monitors for Lithography.................... 32
3.4.1 A Strehl Ratio Test for Process Variation (PV) Band Calibration .............................. 32
3.4.2 Using the Pattern Matcher to Optimize RO Monitor Design ...................................... 33
3.5 Specific Designs for Etch and Lithography Monitors ........................................................ 34
3.5.1 RO Monitors for Etch Dependence of Poly................................................................. 34
3.5.2 RO Monitors for Focus Dependence of Poly............................................................... 35
3.5.3 RO Monitors for Gate-to-Active Overlay Using Pre-Programmed Offsets ................ 36
3.6 Designing Nitride CESL-Induced Strain and STI-Induced Stress RO Monitors ............... 39
3.7 Summary............................................................................................................................ 40
Chapter 4: 45nm Ring Oscillator Testing methodologies and Noise Analysis ............................ 41
4.1 Automated RO Frequency Measurement Setup and Testing Methodologies..................... 41
4.1.1 An overview of the RO Frequency Measurement Test Setup ..................................... 41
4.1.2 Adjustment of Operating Voltages and Temperatures................................................. 43
4.1.3 RO Measurement Sequence......................................................................................... 44
4.2 Measurement System Noise and Drift ................................................................................ 45
4.2.1 RO Measurement Jitter ................................................................................................ 45
4.2.2 RO Measurement Drift ................................................................................................ 46
4.3 Measured Block-to-Block Variation................................................................................... 48
4.4 Measured Across-Wafer Variation ..................................................................................... 50
4.5 Summary ............................................................................................................................. 55
Chapter 5: Experimental RO Frequency Sensitivity to Gate Etch, Gate Lithography Focus, and
Gate-to-Active Overlay................................................................................................................. 56
5.1 Simulated RO Frequency Variability using Process Corners and Process Variation Bands
.................................................................................................................................................. 56
5.1.1 Simulated Process Corners versus Measured RO Frequencies.................................... 57
5.1.2 PV Bands and SPICE Simulations versus Measured RO Frequency .......................... 57
5.2 RO Frequency Sensitivity to Gate Etch .............................................................................. 58
5.2.1 Measured RO Frequency Sensitivity to Gate Etch ...................................................... 58
5.2.2 Simulated RO Frequency Sensitivity to Gate Etch using Process Corners ................. 60
5.2.3 Simulated RO Frequency Sensitivity to Gate Etch Monitors using PV Bands and
SPICE................................................................................................................................... 62
v
5.3 RO Frequency Sensitivity to Gate Lithography Focus ....................................................... 62
5.3.1 Measured RO Frequency Sensitivity to Gate Lithography Focus ............................... 63
5.3.2 Simulated RO Frequency Sensitivity to Gate Lithography Focus using Process
Corners................................................................................................................................. 65
5.3.3 Simulated RO Frequency Sensitivity to Gate Lithography Focus using PV Bands and
SPICE................................................................................................................................... 66
5.3.4 Across-Wafer Correlation Plots................................................................................... 67
5.4 RO Frequency Sensitivity to Gate-to-Active Misalignment............................................... 68
5.5 Summary............................................................................................................................ 69
Chapter 6: RO Frequency Sensitivity to Nitride CESL and STI-Induced Stress ......................... 71
6.1 RO Frequency Sensitivity to Nitride CESL-Induced Strain ............................................... 71
6.1.1 RO Frequency Sensitivity versus LOD’ ...................................................................... 72
6.1.2 Measured RO Frequency Distributions for Two Different 45nm Tapeouts ................ 74
6.1.3 RO Frequency Sensitivity Averaged Across 15 Typical Chips versus LOD’............. 75
6.1.4 RO Frequency Sensitivity to Asymmetrical Source/Drain.......................................... 75
6.1.5 RO Frequency versus Mobility and Injection Velocity Models .................................. 77
6.2 RO Frequency Sensitivity to STI-Induced Stress ............................................................... 78
6.3 Summary............................................................................................................................ 79
Chapter 7: Random Noise Analysis: Gate Length, Gate Oxide Thickness, and Doping Variation
...................................................................................................................................................... 81
7.1 Quantile-Quantile (QQ) and Autocorrelation Plots of RO Frequency Measurements ....... 81
7.1.1 QQ Plots....................................................................................................................... 82
7.1.2 The Autocorrelation Plots ............................................................................................ 83
7.2 Block-to-Block Analysis for Outlier Chips ........................................................................ 84
7.3 RO Frequency Sensitivity to Operating Voltages (V
Extraction.............................................................................................................................................. 88
7.4.3 The Matrix Definitions ................................................................................................ 88
7.4.4 The Least Mean Square Solution................................................................................. 89
vi
7.5 Error Analysis for the LMS Solution.................................................................................. 92
7.6 Summary............................................................................................................................ 94
Chapter 8...................................................................................................................................... 95
8.1 Design ................................................................................................................................ 95
8.2 Measurement Methodology ................................................................................................ 96
8.3 Initial Measurement Results ............................................................................................... 96
8.4 Monitoring of Gate Etch, Gate Lithography, and Gate-to-Active Misalignment............... 97
8.5 Monitoring of Nitride CESL and STI-Induced Stress ........................................................ 98
8.6 Random Noise Analysis using Least Mean Squares........................................................... 98
8.7 Overall Perspective ............................................................................................................. 99
Bibliography ............................................................................................................................... 102