How to synthesize register array?

caomin1984 · 发表于 2010-12-6 03:07:46

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Does anybody know how Design Compiler synthesize register array in Verilog model?

Does it use its proprietary model in this regard?

Thanks

shuj102 · 发表于 2010-12-8 19:51:29

I think it will just synthsis into registers, DesignWare has some register array, but actually netlist should be registesr, not RAM

icray · 发表于 2010-12-8 21:19:01

register array means real register array or the ram area, if it is real register array, the register size would increase fast when the register size increase, so it is suitable for small register array. for large register array, we all use the ram which is not be synthesizable.

yx.yang · 发表于 2010-12-9 00:39:13

DC can synthesis it.

XIAOZZ · 发表于 2011-1-14 21:07:56

利用MC生成register file 然后将db文件加入DC就可以综合了

qingwatiaowu · 发表于 2011-4-27 13:39:04

回复 3# icray

借问:

带有这样register array结构的综合网表,到后端布局布线阶段,有没有'特别'的设置,可以'更有效'的利用布线资源?

望有人解答.谢谢

bruce1914 · 发表于 2011-4-28 01:14:09

要看数组的读写电路是怎么写的

[求助] How to synthesize register array?

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