针对IIC主要是slave 的几个例子，verilog编写

roger_155 · 发表于 2011-8-16 20:46:01

01.module div3

02.( input clk,

03.input rst_n,

04.input [7:0] data,

05.output reg flag

06.);

07.

08.reg [3:0] sum;

09.

10.integer i;

11.

12.always @ *

13.begin

14.sum = 0;

15.for (i=0;i<8;i=i+1)

16.begin

17.if (i==0 || i==2 || i==4 || i==6 )

18.sum = (data[i]) ? sum + 1 : sum;

19.else

20.sum = (data[i]) ? sum + 2 : sum;

21.end

22.end

23.

24.always @ (posedge clk, negedge rst_n)

25.begin

26.if (!rst_n)

27.flag <= 1'b0;

28.else if (sum ==0 || sum ==3 || sum==6 || sum==9 || sum==12)

29.flag <= 1'b1;

30.else

31.flag <= 1'b0;

32.end

33.

34.endmodule;