在线咨询
eetop公众号 创芯大讲堂 创芯人才网
切换到宽版

EETOP 创芯网论坛 (原名:电子顶级开发网)

手机号码,快捷登录

手机号码,快捷登录

找回密码

  登录   注册  

快捷导航
搜帖子
查看: 2495|回复: 6

[招聘] 招聘模拟数字IC及应用工程师(实习生)

[复制链接]
发表于 2010-11-28 11:26:02 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

x
本公司现招聘如下工程师(实习生):

Position title: Analog Engineer

Vacancies: 2

Position Responsibilities:

1. Design analog circuits, such as Amplifier, Comparator, ADC/DAC, PLL, CDR, Bandgap, LDO, Filter, Tranceiver, PAD and etc;
2. Use Cadence EDA tool to run simulation;
3. Chip debugging and testing;
4. Design and optimize chip layout.

Position  Requirements:
1. MS degree in ME/EE;
2. Familiar with Cadence design tools for circuit design and simulation;
3. Familiar with the layout drawing tools, layout skills and verification flow;



4. Familiar with ESD, Latch-up and chip reliability design;


5. Familiar with packaging, testing and debugging;

6. Familiar with the semiconductor manufactural process and device knowledge;

7. Familiar with the theory and design methodology of CMOS circuits;

8. At least familiar with one of the following blocks: Amplifier, Comparator, ADC/DAC, PLL, CDR, Bandgap, LDO, Filter, Tranceiver;

9. 2+ years of analog design experience;

10. Good English reading skills.

Position Title: Digital IC design engineer
Vacancies: 6

Position Responsibilities:

1. RTL level coding according to the requirement from analog/system designer;
2. Develop and execute simulation and lab verification plan;
3. Participate in the FPGA platform development and lab debugging;

4. Synthesize RTL code and Place&Route layout automatically.

Position Requirements:

1. MS degree in EE/CE;
2. Good knowledge of RTL design and simulation;
3. Able to write C code to model RTL blocks for simulation and verification;
4. Able to write reusable Verilog RTL codes, follow design and DFT guidelines;
5. Able to run synthesis, static timing analysis and formal verification is

highly desirable, but not required;
6. Experience in Cadence IC Place&Route Layout tool set;

7. 2+ years of digital design experience;

       8. Good English reading skills.

Position Title: Application engineer

Vacancies: 2

Position Responsibilities:

1. IC verification with FPGA and PCB board;

2. Design and debug PCB board;

3. Deliver reference designs, including hardware, software and documentation;

4. Support customer product development.

Position Requirements:

1. MS degree in EE;

2. Have knowledge and experience in FPGA, PCB design and debug, software development;

3. Good English reading skills.

发表于 2010-11-28 18:42:28 | 显示全部楼层
谢谢分享
发表于 2010-11-28 19:47:23 | 显示全部楼层
水水更健康。。。
发表于 2010-11-28 23:46:31 | 显示全部楼层
LZ,联系方式呢?
发表于 2010-11-29 10:38:26 | 显示全部楼层
有意者请站内发消息回复。谢谢
发表于 2010-11-29 13:07:09 | 显示全部楼层
回复 5# winzi


    什么公司,楼主留下联系方式
 楼主| 发表于 2010-11-29 13:09:51 | 显示全部楼层
昆山芯视讯电子科技有限公司。
邮件请发到yumeng@visilicon.com
谢谢!
您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐 上一条 /1 下一条

小黑屋| 手机版| 关于我们| 联系我们| 在线咨询| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2024-11-5 16:30 , Processed in 0.020204 second(s), 7 queries , Gzip On, Redis On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表