Advanced_Verification_Techniques

wolfhunterhu

The last few years in the electronics industry have seen three areas of explosive
growth in design verification. The first 慹xplosion?has been the tremendous
increase in verification requirements for IC抯?ASICs?ASSPs?System-on-Chip
(SoCs) and larger systems. This has been compounded by the rapid increase in use
of embedded processors in these systems from the largest network infrastructure
boxes all the way down to consumer appliances such as digital cameras and wireless
handsets. With processors deeply embedded in systems?verification can no
longer remain solely focused on hardware?but must broaden its scope to include
hardware-dependent software co-verification?and large components of middleware
and applications software verification in the overall system context.
The second area of explosive growth has been in the number and variety of verification
methodologies and languages. New concepts including transaction-based
verification (TBV)?transaction-level modelling (TLM)?and assertion-based verification
(ABV) have arisen to complement the already-extensive verification engineer抯
toolbox?These new verification approaches are not just theoretical - they
have been growing in their application to solve practical and vital verification problems.
Complementing the new verification approaches has been a rapid growth in
verification languages - first?specialized Hardware Verification Languages (HVLs)
such as Verisity抯 慹?(now being standardized by the IEEE 1647 working group);
Synopsys Vera (now subsumed in SystemVerilog) and Cadence Testbuilder (a C++
extension class library and methodology?now largely subsumed in the SystemC
verification library (SCV)). The HVLs as stand-alone notations and languages provided
substantial increases in verification quality and functional coverage?and have
led rather naturally to the idea of an integrated Hardware Design and Verification
Language (HDVL). These include pioneering experiments such as Co-Design
Automation抯 SUPERLOG (now subsumed in SystemVerilog)?Accellera抯 development
of SystemVerilog (to be donated to the IEEE 1364 committee in summer 2004
for standardization as part of Verilog evolution)?and Open SystemC Initiative抯
(OSCI) SystemC. SystemC is a particularly interesting example of an HDVL -
starting off with a Register-Transfer Level (RTL) design language in C++ with SystemC
1.0?extending the language to generalized system modelling with SystemC
2.0?and adding the SystemC Verification Library (SCV) in 2003 to form a full
揝MDVL - System Modelling?Design?and Verification Language? Compounding
the alphabet soup of HDLs and HVLs are the assertion and property libraries and
languages - Open Verification Library (OVL)?OpenVera Assertions (OVA)?and
Accellera抯 Property Specification Language (PSL) and System Verilog Assertions
(SVA).
The third explosion in verification is one that is just starting - the growing availability
of books full of guidance and advice on verification techniques?verification languages?
verification tools?and ways of bringing them all together into a coherent
verification methodology and process. This new volume?Advanced Verification
Techniques?A SystemC Based Approach for Successful Tapeout?by Leena Singh?
Leonard Drucker and Neyaz Khan?is unique among all the books on verification
that are now exploding into existence. As such?it belongs on the shelf of every
design and verification engineer - but?much more than being 搊n the shelf?it
belongs on the desk of every engineer?preferably opened to a relevant page of verification
guidance or knowledge which is being pressed into active service.
What makes this book especially important and unique is that it is the first verification
book which gives detailed insights into C/C++ based verification methods?by
focusing on the usage of TestBuilder and the SystemC Verification library (SCV).
In fact?the book by Singh?Drucker?and Khan has some of the earliest examples in
print of SCV used in action. It covers all the major processes involved in a modern
functional verification methodology?and thus complements earlier books concentrating
on verification tools?and design and verification languages.
SystemC and C++ are particularly good bases on which to build a verification
approach. The use of C++ allows linkages to be built between all participants in the
design and verification process. System-level architects can build early algorithmic
xvi Advanced Verification Techniques
and architectural models at high levels and transaction levels which are useful both
for establishing system level performance characteristics?and for acting as golden
models during downstream verification processes. The scenarios which stress the
system at a high level can become corner cases for functional correctness. The use
of C++ as a base allows for easier reuse of testbenches and models between all participants
in the process. C++ allows easy integration of instruction set simulators?
so hardware-software co-verification becomes an attribute of the verification process.
Data type abstraction?templating and other abstraction features offered by
C++?SystemC?Testbuilder and SCV all contribute to verification productivity?
reuse?coverage and quality.
Advanced Verification Tecniques?A SystemC Based Approach for Sucessful Tapeout?
after an introduction to verification and the overall book?discusses the verification
process in chapter 2?and then follows that with an extensive introduction to the
use of SCV. Chapter 4 discusses the development of the functional verification
testplan?which consolidates the goals?methods and detailed implementation of the
verification requirements into a comprehensive plan for verifying a design. Chapter
5 describes in detal the basic concepts of modern testbenches?and links them to
SystemC. This includes detailed guidance on linking SystemC testbenches to RTL
designs using HDLs. Chapter 6 gives a good overview of transaction based verification
methodology and explicit examples of putting this into practice in creating
testbenches. These three chapters?4-6?give a very clear message - verification of
design is not an afterthought; it is a process that must be planned in advance?before
designers start their work; be well-architected; have clear goals and well laid out
methods to achieve them; and?deserves as much attention as the design process
itself.
Special chapters?7-10?discuss particular important topics in the verification
domain. Regression?for example?is the backbone of a high-quality verification
process as the design and verification tasks proceed. Regression allows the design
to proceed and gives a mechanism for ensuring that design changes move in a positive
direction. Regression adds tremendous confidence to a design team and its
management?so that the decision to move onto detailed implementation?and the
decision to release a design to manufacturing?are based on science?not just gut
feelings and art.
Functional coverage complements the use of regression in ensuring adequate verification
has taken place. Chapter 8 on functional coverage gives a good overview of
this topic and specific guidelines and examples on how to apply it. A further chapter
on memory modelling gives an introduction to an important aspect of verifica-
Foreword xvii
xviii Advanced Verification Techniques
tion that is often overlooked in these kinds of books. This is followed by a
discussion?in the final chapter?on post-synthesis verification at the gate level?
which also deals with functional testing and ATE (automated test equipment) -
again?important pragmatic topics which are often ignored if one were focused
entirely on front-end verification.
Complementing the guidelines and advice in the book are extensive examples in
both Testbuilder (which can be regarded as the first or an early generation of SystemC抯
Verification library) and SCV?and based on two example designs - one from
networking and one from multimedia. These give an excellent and pragmatic illustration
of how to apply the methods?languages and tools in practice. The important
thing about the examples is that they are drawn from real development work of real
designs?and thus proven in anger.
To sum up?the new book from Singh?Drucker and Khan is an important milestone
in the development of C/C++-based verification methods?and I recommend it
highly to anyone who wishes to learn about verification within a C++-based context.
We can expect further use of SystemC verification?and this book will help all
those who want to apply these methods to their practical design verification problems
on a daily basis.

mtwumtwu

good reference for verification !!!

zh123456789

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whitedragon10

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whitedragon10

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gaconht

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nslnsl

bucuo!!!!

lujunfeng111

这3个附件都是论文吗？

alenanderson

Thanks for sharing

abnerchang

Excelletn