Analog Layout Synthesis: A Survey of Topological Approaches

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Part I Placement
1 Device-Level Topological Placement with Symmetry Constraints. . . . .. . . . . . . . . . . 3
Florin Balasa
2 Hierarchical Placement with Layout Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Mark Po-Hung Lin and Yao-Wen Chang
3 Deterministic Analog Placement by Enhanced Shape Functions . . . . . . . . . . . . . . . 95
Martin Strasser, Michael Eick, Helmut Graeb,
and Ulf Schlichtmann

Part II Routing
4 Routing Analog Circuits . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
G¨unhan D¨undar and Ahmet Unutulmaz

Part III Layout in the Design Flow
5 Analog Layout Retargeting . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . .205
Hazem Said, Mohamed Dessouky, Reem El-Adawi,
Hazem Abbas, and Hussein Shahein
6 Closing the Gap Between Electrical and Physical Design:
The Layout-Aware Solution. . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . .243
Rafael Castro-L´opez, Elisenda Roca, and Francisco V.
Fern´andez
7 Constraint-Driven Design Methodology:
A Path to Analog Design Automation.. .  . . . . . . . . . . . . . . . . . . . . . . . . . .269
G¨oran Jerke, Jens Lienig, and Jan B. Freuer
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299

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