哪位大虾指正一下错误在哪？

jerrymeng

是一个mux，不过是1 to 4的
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux41 is
port(x,s0,s1:in std_logic;
      a,b,c,dut std_logic);
end mux41;
architecture mux_arch of mux41 is
signal indata:std_logic_vector(1 downto 0);
begin
indata<=s1&s0;
process(indata)
begin
   case indata is
   when "00" => a=<x;
   when "01" => b=<x;
   when "10" => c=<x;
   when "11" => d=<x;
   when others => a<='0';b<='0';c<='0';d<='0';
end case;
end process;
end mux_arch;