马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。
您需要 登录 才可以下载或查看，没有账号？注册
x
本帖最后由 IC之源 于 2011-1-9 18:34 编辑
以下两个职位分别是设计验证工程师和验证工程师，工作地点是成都。 请有兴趣的朋友和我联系，简历发送到我的邮箱里，谢谢。 harryhahn@hotmail.com •Job Description Position title: SoC ASIC Design/Verification Engineer –Responsibilities: o Integration of ARM processor/DSP co-processor and AMBA bus for SoC; o Integration of H264 Codec , DDR, USB and PCIe etc for SoC; o Design/verification of video surveillance and audio & voice processor with integrated CODEC and amplifier o Design SoC-level logic including clock, reset, and DFT; o Verification of AMBA-based DMA, Memory Subsystem, and all peripheral interfaces at unit level and SoC level o Work with analog group and physical layout team on analog macro integration and synthesis/timing analysis. –Qualification: o 5+ years experience on SoC design and integration; o Hand-on experience in ASIC flow; o Experience of ARM/DSP/AMBA integration and/or verification; o Experience of DMA design and/or verification; o Experience of H264 Codec & DDR SoC integration and verification o Experience of video surveillance project design and verification o Experience of design/verification for audio & voice processor with integrated Codec and amplifiers is a big plus o Domain knowledge on Nand Flash Controller, USB, and PCIe is a plus o DFT (Memory BIST and scan) design background is a plus
• Job Description
–Position title: SoC ASIC Verification Engineer –Responsibilities: o Instrumental in the development of infrastructure for the validation of ARM/DSP AMBA-based architectures and the verification of SoC hardware. o Additional duties include the development of directed and random hardware verification environments, and the application of those environments to SOC verification o Integration of VIP UVC and functional verification agents in OVM/UVM verification environment to support coverage-driven verification –Qualification: o Extensive Verilog experience with SOC verification environments. o Verification experience on ARM/DSP, AXI, and DMA with VIP UVC o Experience developing bus functional models, monitors, scoreboards, generators, functional coverage models o Experience with high level verification languages such as SystemVerilog, OVM or VMM, Vera or Specman, and strong C++ programming background o Shell scripts and Perl expertise, create runsim, lsf, regression management scripts o Able to understand Verilog RTL code, debug simulation errors, identify and fix RTL/Environment issues o Experience of design/verification for audio & voice processor with integrated Codec and amplifiers is a big plus | 
/1 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2010-10-9 12:39:57
楼主