上海著名外企Atheros招聘！Update

mcmm

All positions are available in Shanghai only.
Relocation is not provided.
If you are interesed with these positions, please email your resume to noagain#hotmail.com. Enquries are welcome.
Thank you for your time.
Generally, package will be >=12K for experienced engineers and largely depends on your experience.

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ASIC Design Engineer . Shanghai
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QUALIFICATION (DETAIL):
Education:
BS in Electrical/Electronics Engineering, MS preferred.
Experience:
3 years experience with Verilog programming, logic synthesis and gate
timing. A proven record of delivering successful ASIC's to the market is
preferred.
One or more advantages as following are highly desirable: A strong
background in digital communication, signal processing and networking
protocols; IC Design experiences in wireless communications and audio
processing; Experiences with ARM/DSP, AHB bus and External interface
development.
Good communication skills in English.
Experience in Bluetooth chip design a plus
Must be proficient in RTL coding, logic synthesis, gate-level simulations.
Good knowledge of IC design backend flows.
Experiences in IC life-cycle from conception, design, verification,
top-level netlist with pads to tape-out, chip-testing and mass-production.
FPGA, PCB or embedded SW skill is a plus.
DESCRIPTION OF FUNCTION & RESPONSIBILITY:
The Digital Design Engineer will be responsible for designing our wireless and
SOC ASIC's. You will work closely with our architecture/algorithm engineers to
explore ideas for next generation products and then develop RTL to tern these
ideas into customer solutions.
Chip features specification and RTL design
Synthesis, verification, timing.
FPGA emulation, lab validation and debugging.
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Digital Design Verification Engineer Shanghai
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DESCRIPTION OF FUNCTION & RESPONSIBILITY:

Develop reusable block-level and system-level ASIC testbenches using
Digital Design Verification Engineer
DESCRIPTION OF FUNCTION & RESPONSIBILITY:

Develop reusable block-level and system-level ASIC testbenches using
Systemverilog

Develop new ASIC verification environments to support ASIC
development.

Maintain existing ASIC verification environments.

Define and develop application tests required to verify Asics meet
functional and performance goals.

Define and implement functional/code coverage plans.

Develop testing and regression methodologies for new verification flow.

Develop/maintain/enhance environment tools/scripts/makefiles.
EDUCATION:
Master's degree from first rate engineering schools is preferred.
EXPERIENCE:

Minimum of 3 years ASIC Verification experience in a product
development environment

Proven ASIC Design Verification skills

Rich experience with Specman or System Verilog

Digital verification experience on MIPS CPU/AXI/DDR Controller

Knowledge of data and telecommunication networking(IP/Ethernet)

Experience with one or more scripting languages: TCL, Perl, python

Superior debugging skills for large ASIC designs

Strong written and verbal communication skills

Adaptable to evolving customer requirement

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;; Sr digital verification engineer
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QUALIFICATION (DETAIL):
Education:
Master's degree from first rate engineering schools is prefered.
Experience:

Develop reusable block-level and system-level ASIC testbenches using
Systemverilog

Develop new LOM ASIC verification environments to support ASIC development.

Maintain existing ASIC verification environments.

Define and develop application tests required to verify ASICs meet functional and
performance goals.

Define and implement functional/code coverage plans.

Develop testing and regression methodologies for new verification flow.

Develop/maintain/enhance environment tools/scripts/makefiles.
DESCRIPTION OF FUNCTION & RESPONSIBILITY:

Minimum of 6 years ASIC Verification experience in a product development
environment

Proven ASIC Design Verification skills

Rich experience with Vera/Specman E or SystemVerilog

Digital verification experience on MIPS CPU/AXI/DDR Controller

Knowledge of data and telecommunication networking(IP/Ethernet)

Experience with one or more scripting languages: TCL, Perl, python

Superior debugging skills for large ASIC designs

Strong written and verbal communication skills

Adaptable to evolving customer requirementv.
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New Grads recruiting for physical design engineer
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QUALIFICATION (DETAIL):
Education:
BSEE or MSEE
Experience:
1. Knowledge of any part of the process from netlist handoff to tapeout is a MUST:
Floorplanning
Power planning and signoff
Placement, CTS and routing
SI effect analysis and fixing
Physical verification
2. Hands-on experience on above items is preferred.
3. Scripts development in Perl and TCL
DESCRIPTION OF FUNCTION & RESPONSIBILITY:
1. Implement APR from netlist to gds to close timing and routing
2. Build high efficient PG mesh to meet IR-drop and EM requirements
3. Fix SI effect
4. Perform ECO and metal spin
5. Support die size estimation
6. Develop utilities/scripts to improve design flow
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Physical design engineer
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QUALIFICATION (DETAIL):
Education:
BSEE with 2+ years of related experience, MSEE with 1+ years of related experience
Experience:
1. Hands-on experience of any part of the process from netlist handoff to tapeout:
Floorplanning
Power planning and signoff
Placement, CTS and routing
SI effect analysis and fixing
2. Physical verification is a MUST
3. Scripts development in Perl and TCL
DESCRIPTION OF FUNCTION & RESPONSIBILITY:
1. Implement APR from netlist to gds to close timing and routing
2. Build high efficient PG mesh to meet IR-drop and EM requirements
3. Fix SI effect
4. Perform ECO and metal spin
5. Support die size estimation
6. Develop utilities/scripts to improve design flow
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Senior Application Engineer
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QUALIFICATION (DETAIL):
Education:
BS/MS degree in Electrical Engineering, or related field
Experience:

5+ years of applicable work experience on board design.
Strong problem-solving skill to isolate and resolve issue
Experience with HW board design for switch/router/networking/
Familiar with SI and EMI design.
DESCRIPTION OF FUNCTION & RESPONSIBILITY:

Support customer to resolve issue for switch product line.

Guide customers for schematics and layout design

Writing tech documents including datasheet, app notes and schematics and layout
guideline etc

Define and design reference and demo board

Responsible for system level HW test and support

Provide detailed technical training to FAE and customers

Help product definition with field feedback

mcmm

up up up!!

nowich

谢谢分享~~~

gbq

eetop good

tigernk

社会招聘还是校园招聘啊？