about post-layout verifcation

dongdong214

hi
please tell me what have the 'prime time' done during the post-layout verification? on other words,why the 'prime time' can verify the final design of the chip?
what job can be sure the functionlity of the chip after place and route,why?   
you can send me document,chnn51@yahoo.com
thanks a lots.

jingli888ca

Hello,
PT does not verify the function of your design. It simply check if the timing of your design meet your constraints.
The assumption is that functional verificaiton is done already on the RTL level. Then as long as the PAR netlist meet the timing, then it is OK to tape out.

phase2000

i think if you have library of standard cell, then according *.spf , you can do it.

laydesign

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