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本帖最后由 nothinglee 于 2011-10-21 17:52 编辑
开放的职位有前端SOC，DFT，P&R, Memory Compiler Engineer
DFT和PR的具体要求我就不写了，做过的都知道，至少3年以上经验。
PR分IBM flow和COT flow，会Synopsy Cadence IBM工具的都可以。
暗戳戳的说一句：明年可能上市。小道消息，不保证准确哦。
班车，免费午餐，补充医疗保险，旅游等福利，总体还是不错的。
有意者发送简历到： xiaoxuanwo5858@163.com
最近陆续收到不少朋友的简历。符合条件的都陆续面试了。
这些职位是需要至少3年以上的直接经验的，因为是给客户做设计服务，那么首先自己要比较有经验才可以。
所以刚毕业和资历比较浅的同学暂时不考虑哦，有些不符合条件的同学我邮件回复了~~虽然我也从菜鸟过来，但毕竟目前职位要求是直接经验。
大家提到的待遇嘛，我只能说如果合适，不会比trident Amd cadence 等所谓大公司差。
下面是SOC和Memory Compiler的要求：
SOC logic design Engineer/Sr. Engineer
Responsibilities:
1.
Play an important role in defining chip spec and advising chip architure
2.
Develop challenging modules including module spec definition, macro architecture design,RTL coding, simulation and synthesis
3.
Carry out chip level verification on chip integration/implementation
4.
Help junior engineers to solve technical issues
5.
Support customers regarding chip applications
Requirements:
1.
Bachelor degree or above in EE
2.
Good knowledge of some of the following general IP: CPU/DSP, AMBA, memory controller, parallel/serial peripheral module, DMA, interrupt, timer, GPIO and so on
3.
Good skill in the field of digital circuit design, whole design flow and EDA tools
4.
Key member in at least on successfully silicon proven challenging project
5.
Fluent in both English and Chinese
6.
Self motivated, good communication skill and team work spirit
Memory Compiler Engineer
Responsibilities:
1.
Develop, debug and maintain memory compiler software for different memory designs and structures
2.
Characterize memory and generate front-end models, including Synopsys, Verilog, DFT etc.
3.
Maintain and customer support for memory compiler related issues.
Requirements:
1.
Minimum BS degree in EE/CS or related majors
2.
Skillful on C/C++ language and experience at C/C++ programming. Ability of develop and debug software on UNIX/Linux platform
3.
Familiar with X-window Motif/TCL GUI development
4.
Familiar with Verilog, CDL, GDSII, Synopsys Liberty timing model, LEF, antenna CLF, MBIST models
5.
Know of Layout Design rules |
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发表于 2010-8-26 10:52:16
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