DESIGN OF A DELAY-LOCKED LOOP WITH A DAC-CONTROLLED ANALOG DELAY LINE

angelweishan

DESIGN OF A DELAY-LOCKED LOOP WITH A DAC-CONTROLLED ANALOG DELAY LINE

1 Introduction ……………………………………………………………………… 1
1.1 Motivation …………………………………………………………………. 1
1.2 Ideal DLL Operation ………………………………………………………. 2
1.3 Non-Ideal Considerations …………………………………………………. 5

2 Current DLL Designs ……………………………………………………………. 7
2.1 Digital DLL ……………………………………………………………….. 7
2.2 Analog DLL ………………………………………………………………. 11
2.3 Dual-Loop DLL …………………………………………………………... 12
2.4 Synchronous Mirror Delay ……………………………………………….. 12

3 DLL Design ……………………………………………………………………... 15
3.1 Process and Simulation Models …………………………………………... 15
3.2 Proposed Design ………………………………………………………….. 15
3.3 Delay Line Design ………………………………………………………... 18
3.4 Current Reference Design ………………………………………………... 24
3.5 DAC Design ……………………………………………………………… 26
3.6 DAC Performance ………………………………………………………... 35
3.7 Up/Down Counter Design ………………………………………………... 42
3.8 Phase Detector Design ……………………………………………………. 48
3.9 DLL Control Circuitry ……………………………………………………. 54
3.10 Full System Design ……………………………………………………….. 59

4 DLL Performance ……………………………………………………………….. 60
4.1 Operation ………………………………………………………………….. 60
4.2 Performance Characteristics ………………………………………………. 62

5 Conclusions ……………………………………………………………………… 66

chujn

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leonken460

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momo166

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xlteam17

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hanbenguang

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xlteam2

very good

mainhand

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qqgomy

谢谢分享~~~

whp2203

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