请高手诊断，时钟域问题 付代码

wbs605697131

//*************TEMP Detection************//
module TEMP_Detection ( Value,Max6577_Clk,FPGA_Clk,Rst);//,INSIDE_Clk);
input Max6577_Clk;
input FPGA_Clk;   //77.76M hz
input Rst;    //要是有汉字呢？
output [15:0] Value;
   //output INSIDE_Clk;      //This is 0.5HZ clk
reg [15:0] Value;
integer temp;
reg [15:0] temp2;
reg INSIDE_Clk;   //0.5 hz
parameter INPUT_FREQ = 32'd77759999;   // Provide by  the outside     77.76M - 1 = 77759999

//    Generate the Rst
always @ ( posedge Rst or posedge FPGA_Clk )
if ( Rst )   temp <=0;
else if ( temp < INPUT_FREQ )  temp <= temp + 16'b1;   //77759999   
else  temp <= 16'b0;
//    Generate  the  INSIDE_Clk(0.5 hz)  ,which is by the 77.76Mhz clk
always @ ( posedge Rst or posedge FPGA_Clk )
if ( Rst ) INSIDE_Clk <= 1;
else if ( temp == INPUT_FREQ )  INSIDE_Clk <= ~INSIDE_Clk;

////// Generate the Value
always @ ( posedge Max6577_Clk or posedge Rst)
if ( Rst )   temp2 <= 16'b0;
else if (INSIDE_Clk) temp2 <= temp2 + 16'b1;
else temp2 <= 16'b0;
  
always @ ( negedge INSIDE_Clk or posedge Rst)
if ( Rst )        Value <= 16'b0;
else Value <= temp2;  
endmodule


老板说不能用INSIDE_Clk控制D触发器这么的，请问问题在哪啊？