BIST Circuit for Pipelined Analog to Digital Converter

angelweishan

Built-in Self-test Circuit for Pipelined Analog to Digital Converter

研究生: 任慶霖  ChingLin Jang
指導教授: 蘇朝琴  ChauChin Su

Chapter 1 Introduction  1
1.1 Motivation          1
1.2 Thesis Organization      2

Chapter 2 Fundamentals of Pipelined ADC  .4
2.1 Introduction        .4
2.2 The Principles of Pipelined ADC      5
2.3 Errors in Pipelined ADC              9
2.3.1 Nonlinearity in SubADC          .9
2.3.2 Offset error in SubDAC            10
2.3.3 Gain Error in residue amplifier        .10
2.4 Digital Error Correction          12

Chapter 3 The BIST Architecture        17
3.1 Introduction    17
3.2 BIST Introduction      .17
3.3 Probability Analysis on the Errors  18
3.4 Sample Number Analysis              21
3.5 BIST Architecture      .23
3.6 Comparator Offset Calibration          24
3.7 Triangular Wave Generator Linearity    25
3.8 Triangular Wave Generator Circuit      28
3.9 Error Count Reference (Matlab Simulation)  30
3.10 Correction      31

Chapter 4 A 8-bit 100MS/s CMOS Pipelined ADC    33
4.1 Introduction    33
4.2 Capacitor Selection  34
4.3 Sample and Hold Circuit              .35
4.3.1 S/H Circuit      .35
4.3.2 Bootstrapped Switch          35
4.4 MDAC          .37
4.4.1 MDAC Selection          37
4.4.2 MDAC Circuit            38
4.4.3 Intentional Stage Gain Error      38
4.5 OP Specification      39
4.5.1 OP consideration in S/H          39
4.5.2 OP consideration in MDAC        41
4.5.3 Linearity of OP                .42
4.5.4 OP Design  43
4.6 Comparator      45
4.6.1 Preamp        .45
4.6.2 Low Offset Regenerative Latch        46
4.6.3 Monte Carlo Simulation of Comparator  ..46
4.7 ADC Timing Diagram            49
4.8 Clock Generator      .50

Chapter 5 Simulation Result and Layout    .53
5.1 Introduction    53
5.2 OP Simulation Result                53
5.3 S/H Simulation Result            54
5.4 ADC Simulation Result              55
5.5 ADC with Mismatch    56
5.5.1 Simulation Result of intentional mismatch          56
5.5.2 Simulation Result with Gain Error in Stage 1            57
5.5.3 Simulation Result with Gain Error in stage 1 , 2        58
5.5.4 After Correction with Gain Error in Stage 1              59
5.5.5 After Correction with Gain Error in Stage 1 , 2            .60
5.6 Layout and Measurement Setup      62

Chapter 6 Conclusions          64
6.1 Conclusions    64
Bibliography      .65

aceafee

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chhwang0123

very good material

glacialwang

感謝分享

piao

a good one, thanks for sharing

lyc1981

take a look

langtaosha

感谢共享！！！！

orchild88

感谢您的分享

baoerxing

A good master thesis

potee991

好好！