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本帖最后由 angelweishan 于 2010-7-19 17:12 编辑
Design of High-Performance Time-Interleaved Pipelined Analog-to-Digital Converters
研究生: 李瑞梅
指導教授: 吳介琮
1 Introduction 1
1.1 Motivation . . . . . . . . . .. . . . . . . . . . 1
1.2 Organization of Thesis . . . . . . . . . .3
2 Pipelined ADCs 5
2.1 Introduction . . . . . . . . . . . . . .. . . . . . 5
2.2 Nonidealities in Pipelined ADCs . . . . . . . . . . . 9
2.2.1 Offset Errors . . . . . . . . . . . . . .. . . . 10
2.2.2 Sub-DAC and Interstage Gain Error . . . . . . . .14
2.3 Switched-Capacitor Implementations . . . . . . . . . 16
2.4 Summary . . . . . . . . . . . . . . . . . . . . . .25
3 Techniques for Linearity Enhancement 27
3.1 Introduction . . . . . . . . . . . . . . . . . . . . 27
3.2 Capacitor Error Averaging. . . . . . . . . . . . . . 28
3.3 Foreground Digital Calibration . . . . . . . . . . . 31
3.4 Background Digital Calibration . . . . . . . . . . . 34
3.5 Proposed Background Digital Calibration . . . . . . 38
3.6 Summary. . . . . . . . . . . . . . . . . . . . . . 44
4 Time-Interleaved ADCs 47
4.1 Introduction . . . . . . . . . . . . . . . . . . . . 47
4.2 Overview of Time-Interleaved ADCs . . . . . . 48
4.3 Nonidealities in Time-Interleaved ADCs . . . . . . . 50
4.3.1 Timing Mismatch . . . . . . . . . . . . . . . . 50
4.3.2 Gain Mismatch . . . . . . . . . . . . . . . . . 54
4.3.3 Offset Mismatch. . . . . . . . . . . . . . . . . 57
4.4 Summary. . . . . . . . . . . . . . . . . . . . . . 60
5 Techniques for Reducing TI Mismatch Errors 61
5.1 Introduction . . . . . . . . . . . . . . . . . . . . 61
5.2 Foreground Calibration . . . . . . . . . . . . . . . 61
5.3 Equalization-Based Calibration . . . . . . . . . . . 63
5.4 Randomly Time-Interleaving Method. . . . . . . . . 68
5.5 Proposed Mismatch Correction Technique . . . . . . . 72
5.6 Summary. . . . . . . . . . . . . . . . . . . . . . 77
6 Sample-and-Hold Amplifiers for TI-ADCs 79
6.1 Introduction . . . . . . . . . . . . . . . . . . . . 79
6.2 Flip-Around SHA. . . . . . . . . . . . . . . . . . 80
6.3 Charge-Transfered SHA . . . . . . . . . . . . . 82
6.4 Charge-Redistribution SHA . . . . . . . . . . . 85
6.5 Precharged SHA (PC-SHA). . . . . . . . . . . 87
6.6 Proposed Buffered-Precharged SHA (BP-SHA). . . . . 90
6.7 The PC-SHA and BP-SHA in a TI-ADC. . . . . . . . . 93
6.8 Summary. . . . . . . . . . . . . . . . . . . . . . 99
7 A 15-bit 125 MS/s Time-Interleaved Pipelined ADC 101
7.1 Introduction. . . . . . . . . . . . . . . . . . . 101
7.2 ADC’s Architecture . . . . . . . . . . . . . . . . 101
7.3 Front-end SHA . . . . . . . . . . . . . . . . . . . 102
7.4 Pipelined A/D Channel . . . . . . . . . . . . . . . 106
7.5 Digital Circuits . . . . . . . . . . . . . . . . . 109
7.6 Experimental Results. . . . . . . . . . . . . . . 113
7.7 Summary . . . . . . . . . . . . . . . . . . . . . . 119
8 Conclusions and Future Works 125
8.1 Conclusions . . . . . . . . . . . . . . . . . . . . 125
8.2 Future Works. . . . . . . . . . . . . . . . . . . 126 |
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发表于 2010-7-19 15:46:08
